Dear coreboot folks,
looking at the differences of Intel’s SPI drivers, there is
$ diff -u src/southbridge/intel/{bd82x6x,lynxpoint}/spi.c
--- src/southbridge/intel/bd82x6x/spi.c 2013-06-29 11:54:25.304090457
+0200
+++ src/southbridge/intel/lynxpoint/spi.c 2013-06-29
11:54:25.308090366 +0200
@@ -34,19 +34,18 @@
#define min(a, b) ((a)<(b)?(a):(b))
#ifdef __SMM__
-#include <northbridge/intel/sandybridge/pcie_config.c>
#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pcie_read_config8(dev, reg)
+ *(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pcie_read_config16(dev, reg)
+ *(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pcie_read_config32(dev, reg)
+ *(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
- pcie_write_config8(dev, reg, val)
+ pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
- pcie_write_config16(dev, reg, val)
+ pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
- pcie_write_config32(dev, reg, val)
+ pci_write_config32(dev, reg, val)
#else /* !__SMM__ */
#include <device/device.h>
#include <device/pci.h>
[…]
due to the following commit [1].
commit 89f79a019fd049f26ed7bf40618ff960bd9e095e
Author: Aaron Durbin <[email protected]>
Date: Wed Oct 31 23:05:25 2012 -0500
haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Searching the code for that Kconfig variable, I get the following
results
$ git grep MMCONF_SUPPORT_DEFAULT
src/Kconfig:config MMCONF_SUPPORT_DEFAULT
src/arch/x86/include/arch/io.h:#if CONFIG_MMCONF_SUPPORT_DEFAULT
src/arch/x86/include/arch/io.h:#if CONFIG_MMCONF_SUPPORT_DEFAULT
src/arch/x86/include/arch/io.h:#if CONFIG_MMCONF_SUPPORT_DEFAULT
src/arch/x86/include/arch/io.h:#if CONFIG_MMCONF_SUPPORT_DEFAULT
src/arch/x86/include/arch/io.h:#if CONFIG_MMCONF_SUPPORT_DEFAULT
src/arch/x86/include/arch/io.h:#if CONFIG_MMCONF_SUPPORT_DEFAULT
src/cpu/amd/model_10xxx/Kconfig: select MMCONF_SUPPORT_DEFAULT
src/mainboard/hp/dl165_g6_fam10/Kconfig:config MMCONF_SUPPORT_DEFAULT
src/mainboard/supermicro/h8qgi/Kconfig: #select MMCONF_SUPPORT_DEFAULT
#TODO enable it to resolve Multicore IO conflict
src/mainboard/tyan/s2912_fam10/Kconfig: select MMCONF_SUPPORT_DEFAULT
src/mainboard/tyan/s8226/Kconfig: #select MMCONF_SUPPORT_DEFAULT
#TODO enable it to resolve Multicore IO conflict
src/northbridge/amd/agesa/family10/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/amd/agesa/family15/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/amd/agesa/family15tn/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/amd/amdfam10/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/gm45/Kconfig: select MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/gm45/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/haswell/Kconfig: select MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/haswell/bootblock.c: * setup the PCIEXBAR
because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
src/northbridge/intel/haswell/bootblock.c: *
CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
src/northbridge/intel/haswell/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/i5000/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/i945/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/sandybridge/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/intel/sch/northbridge.c:#if
CONFIG_MMCONF_SUPPORT_DEFAULT
src/northbridge/via/vx900/Kconfig: select MMCONF_SUPPORT_DEFAULT
and I wonder why this option is not selected for more platforms or even
enabled by default (for systems having `MMCONF_SUPPORT`)? Reading the
AMD whitepaper it claims that the Linux kernel can determine if MMIO is
there during runtime [3]. Though I have no idea if that is only possible
because of the firmware setting things up correctly beforehand.
Additionally for Intel systems `MMCONF_SUPPORT` (without `_DEFAULT`)
seems to be selected in each mainboard where for AMD systems it is done
under `src/cpu`.
Thanks,
Paul
[1] http://review.coreboot.org/2618
[2] http://review.coreboot.org/#/c/3502/4/src/southbridge/intel/bd82x6x/spi.c
[3]
http://developer.amd.com/wordpress/media/2012/10/pci%20-%20pci%20express%20configuration%20space%20access.pdf
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