On 12/14/2013 06:08 AM, Paul Menzel wrote: > Dear Dave, dear coreboot folks, > > > hopefully this can be discussed and agreed upon more quickly on the > list. > [...] > > Are there boards in the tree with hard-coded memory > configuration/settings? > Yes. A number of google boards have DRAM chips hardwired, and non-replaceable. Their solution is to read the SPD from CBFS during romstage, before raminit.
>> +config DDR3_SOLDERED_DOWN >> + bool >> + default n > > In my opinion such an option should be introduced globally and not just > for AMD. Especially as the name does not included »AMD«. > And what happens when the board may have more than one SPD. See google/slippy. I think the solution presented here is inelegant, but I'm willing to let it fly. However, since we don't have the patch that adds the mainboard mentioned, we really don't have a way to judge this change. I think this is a hack, and has the potential to turn really ugly, really soon. I want to see the mainboard patch so I can see if this is a well-designed change (R), or if we made this quick hack because we didn't think it over well enough(TM). >> + >> +config PATH_TO_DDR3_SPD >> + string >> + default "" >> + help >> + This is the path from where it is being used/built to where >> + it is stored. > > I have no idea how much data such a file contains. If it is rather small > can it be put into `devicetree.cb` directly? > Devicetree is used in ramstage, but you need the SPD in romstage. > […] > > > Thanks, > > Paul > > > PS: Dave, Bruce, sorry for sending the message to you twice. > > > -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
