Have a look at the power loss control bits inside the superio chip. They
specify what to do when the mainboard gets its standby power.
Okay, but how please?
Haven't read enough of the coreboot source code to be able to say if and
where those bits are written by coreboot.
They are in the LDN A of the SIO chip, bits 5 and 6 in CR E4h. See the
SIO datasheet.
Since VRTC is the power well for that unit of the chip, removing the
power and the BIOS battery for a minute should reset those bits to 0.
Regards
Felix
I wonder why my mail client doesn't use the address the mails from the
mailing list are delivered to as address in the from field...
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