USB


coreboot-4.0-6755-g8128a56 Sat Sep  6 13:18:41 CEST 2014 starting...
PM1_CNT: 00001c00
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 32MB UMA
SMBus controller enabled.
find_current_mrc_cache_local: picked entry 0 from cache block
reg2ca9_bit0 = 0
reg274265[0][0] = 5
reg274265[0][1] = 5
reg274265[0][2] = e
reg274265[1][0] = 5
reg274265[1][1] = 5
reg274265[1][2] = e
[6dc] <= 23faff
[6e8] <= 23faff
USB


coreboot-4.0-6755-g8128a56 Sat Sep  6 13:18:41 CEST 2014 starting...
PM1_CNT: 00001c00
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 32MB UMA
SMBus controller enabled.
find_current_mrc_cache_local: picked entry 0 from cache block
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7f (7f) 67 (67) 82 (82) 
lane 1: 20 (20) 75 (75) 5f (5f) 78 (78) 
lane 2: 20 (20) 88 (88) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4f (4f) 6a (6a) 
lane 4: 20 (20) cc (cc) af (af) ca (ca) 
lane 5: 20 (20) aa (aa) 81 (81) 9c (9c) 
lane 6: 20 (20) bc (bc) 9f (9f) ba (ba) 
lane 7: 20 (20) bc (bc) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 66 (66) 81 (81) 
lane 1: 20 (20) 74 (74) 61 (61) 7b (7b) 
lane 2: 20 (20) 84 (84) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6d (6d) 
lane 4: 20 (20) c9 (c9) ac (ac) c7 (c7) 
lane 5: 20 (20) a7 (a7) 80 (80) 9b (9b) 
lane 6: 20 (20) bb (bb) 9f (9f) ba (ba) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 20 (20) a1 (a1) 6c (6c) 82 (82) 
lane 1: 20 (20) 94 (94) 64 (64) 7c (7c) 
lane 2: 20 (20) ab (ab) 7a (7a) 92 (92) 
lane 3: 20 (20) 8a (8a) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) ce (ce) 86 (86) a1 (a1) 
lane 6: 20 (20) df (df) a1 (a1) b8 (b8) 
lane 7: 20 (20) de (de) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a4 (a4) 6b (6b) 81 (81) 
lane 1: 20 (20) 96 (96) 64 (64) 7b (7b) 
lane 2: 20 (20) ac (ac) 7a (7a) 93 (93) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 88 (88) a2 (a2) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 38 (0)
[10b] = 0 (0)
Couldn't discover DRAM timings (3)
