USB


coreboot-4.0-6755-g8128a56 Sat Sep  6 13:18:41 CEST 2014 starting...
PM1_CNT: 00001c00
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 32MB UMA
SMBus controller enabled.
find_current_mrc_cache_local: picked entry 1 from cache block
reg2ca9_bit0 = 0
reg274265[0][0] = 5
reg274265[0][1] = 5
reg274265[0][2] = e
reg274265[1][0] = 5
reg274265[1][1] = 5
reg274265[1][2] = e
[6dc] <= 23faff
[6e8] <= 23faff
USB


coreboot-4.0-6755-g8128a56 Sat Sep  6 13:18:41 CEST 2014 starting...
PM1_CNT: 00001c00
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 32MB UMA
SMBus controller enabled.
find_current_mrc_cache_local: picked entry 1 from cache block
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 20 (20) 9f (9f) 6c (6c) 83 (83) 
lane 1: 20 (20) 95 (95) 64 (64) 7c (7c) 
lane 2: 20 (20) a9 (a9) 7a (7a) 92 (92) 
lane 3: 20 (20) 88 (88) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 38 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 20 (20) 9f (9f) 6c (6c) 83 (83) 
lane 1: 20 (20) 95 (95) 64 (64) 7c (7c) 
lane 2: 20 (20) a9 (a9) 7a (7a) 92 (92) 
lane 3: 20 (20) 88 (88) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 20 (20) 95 (95) 64 (64) 7c (7c) 
lane 2: 20 (20) a9 (a9) 7a (7a) 92 (92) 
lane 3: 20 (20) 88 (88) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 20 (20) a9 (a9) 7a (7a) 92 (92) 
lane 3: 20 (20) 88 (88) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 20 (20) 88 (88) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 20 (20) ef (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 20 (20) cc (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 20 (20) dd (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 20 (20) dc (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) a3 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 20 (20) 95 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 20 (20) ac (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 20 (20) 86 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 20 (20) ef (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 20 (20) cd (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 20 (20) dd (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 20 (20) dd (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 20 (20) 74 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 20 (20) 87 (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 20 (20) 64 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 20 (20) cc (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 20 (20) a7 (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 20 (20) bb (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 20 (20) 74 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 20 (20) 85 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 20 (20) 63 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 20 (20) c7 (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 15 (20) bc (c7) ab (ab) c6 (c6) 
lane 5: 20 (20) a7 (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 15 (20) bc (c7) ab (ab) c6 (c6) 
lane 5: 13 (20) 9a (a7) 81 (81) 9d (9d) 
lane 6: 20 (20) bb (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 15 (20) bc (c7) ab (ab) c6 (c6) 
lane 5: 13 (20) 9a (a7) 81 (81) 9d (9d) 
lane 6: 12 (20) ad (bb) 99 (99) b4 (b4) 
lane 7: 20 (20) bb (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 7c (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6f (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d2 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a1 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b8 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 15 (20) bc (c7) ab (ab) c6 (c6) 
lane 5: 13 (20) 9a (a7) 81 (81) 9d (9d) 
lane 6: 12 (20) ad (bb) 99 (99) b4 (b4) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 8c (83) 
lane 1: 14 (20) 89 (95) 64 (64) 84 (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 9a (92) 
lane 3: 12 (20) 7a (88) 55 (55) 75 (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d8 (d2) 
lane 5: 12 (20) be (cc) 85 (85) a5 (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) c1 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) b2 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 73 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a3 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ac (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 82 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 80 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 97 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9c (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 15 (20) bc (c7) ab (ab) c6 (c6) 
lane 5: 13 (20) 9a (a7) 81 (81) 9d (9d) 
lane 6: 12 (20) ad (bb) 99 (99) b4 (b4) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 79 (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6e (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d2) 
lane 5: 12 (20) be (cc) 85 (85) 9f (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b9 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a9 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 8c (82) 
lane 1: 14 (20) 89 (95) 65 (65) 85 (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 9b (94) 
lane 3: 12 (20) 78 (86) 59 (59) 79 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d8 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a9 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) c2 (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) b5 (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 87 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 86 (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 9b (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6e (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) d0 (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) a1 (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) ba (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) ab (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 7c (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 93 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 6c (6c) 
lane 4: 15 (20) bc (c7) ab (ab) c6 (c6) 
lane 5: 13 (20) 9a (a7) 81 (81) 9d (9d) 
lane 6: 12 (20) ad (bb) 99 (99) b4 (b4) 
lane 7: 12 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 79 (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6e (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d2) 
lane 5: 12 (20) be (cc) 85 (85) 9f (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b9 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a9 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 71 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a2 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ad (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 12 (20) 70 (7e) 67 (67) 83 (82) 
lane 1: 12 (20) 66 (74) 66 (66) 7f (80) 
lane 2: 13 (20) 7a (87) 7b (7b) 95 (97) 
lane 3: 12 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 14 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 13 (20) 9a (a7) 81 (81) 9b (9c) 
lane 6: 12 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 12 (20) ad (bb) 8b (8b) a4 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 13 (20) 70 (7d) 65 (65) 85 (81) 
lane 1: 11 (20) 65 (74) 62 (62) 82 (7c) 
lane 2: 13 (20) 78 (85) 78 (78) 98 (93) 
lane 3: 12 (20) 55 (63) 51 (51) 71 (6c) 
lane 4: 15 (20) bc (c7) ab (ab) cb (c6) 
lane 5: 13 (20) 9a (a7) 81 (81) a1 (9d) 
lane 6: 12 (20) ad (bb) 99 (99) b9 (b4) 
lane 7: 12 (20) ad (bb) 8b (8b) ab (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 13 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 14 (20) 89 (95) 64 (64) 79 (7c) 
lane 2: 15 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 12 (20) 7a (88) 55 (55) 6e (6f) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d2) 
lane 5: 12 (20) be (cc) 85 (85) 9f (a1) 
lane 6: 13 (20) d0 (dd) a1 (a1) b9 (b8) 
lane 7: 13 (20) cf (dc) 92 (92) a9 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 13 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 14 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 15 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 12 (20) 78 (86) 59 (59) 71 (73) 
lane 4: 12 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 12 (20) bf (cd) 89 (89) a2 (a3) 
lane 6: 13 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 13 (20) d0 (dd) 95 (95) ad (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 5 (20) 70 (7e) 67 (67) 83 (82) 
lane 1: 5 (20) 66 (74) 66 (66) 7f (80) 
lane 2: 6 (20) 7a (87) 7b (7b) 95 (97) 
lane 3: 5 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 7 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 6 (20) 9a (a7) 81 (81) 9b (9c) 
lane 6: 5 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 5 (20) ad (bb) 8b (8b) a4 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 6 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 4 (20) 65 (74) 62 (62) 7b (7c) 
lane 2: 6 (20) 78 (85) 78 (78) 92 (93) 
lane 3: 5 (20) 55 (63) 51 (51) 6d (6c) 
lane 4: 8 (20) bc (c7) ab (ab) c4 (c6) 
lane 5: 6 (20) 9a (a7) 81 (81) 9b (9d) 
lane 6: 5 (20) ad (bb) 99 (99) b4 (b4) 
lane 7: 5 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 6 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 7 (20) 89 (95) 64 (64) 79 (7c) 
lane 2: 8 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 5 (20) 7a (88) 55 (55) 6e (6f) 
lane 4: 5 (20) e1 (ef) b8 (b8) d1 (d2) 
lane 5: 5 (20) be (cc) 85 (85) 9f (a1) 
lane 6: 6 (20) d0 (dd) a1 (a1) b9 (b8) 
lane 7: 6 (20) cf (dc) 92 (92) a9 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 6 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 7 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 8 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 5 (20) 78 (86) 59 (59) 71 (73) 
lane 4: 5 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 5 (20) bf (cd) 89 (89) a2 (a3) 
lane 6: 6 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 6 (20) d0 (dd) 95 (95) ad (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 1 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 5 (20) 70 (7e) 67 (67) 83 (82) 
lane 1: 5 (20) 66 (74) 66 (66) 7f (80) 
lane 2: 6 (20) 7a (87) 7b (7b) 95 (97) 
lane 3: 5 (20) 56 (64) 4e (4e) 6a (6a) 
lane 4: 7 (20) c0 (cc) b0 (b0) ca (ca) 
lane 5: 6 (20) 9a (a7) 81 (81) 9b (9c) 
lane 6: 5 (20) ad (bb) 9a (9a) b5 (b5) 
lane 7: 5 (20) ad (bb) 8b (8b) a4 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 6 (20) 70 (7d) 65 (65) 81 (81) 
lane 1: 4 (20) 65 (74) 62 (62) 7b (7c) 
lane 2: 6 (20) 78 (85) 78 (78) 92 (93) 
lane 3: 5 (20) 55 (63) 51 (51) 6d (6c) 
lane 4: 8 (20) bc (c7) ab (ab) c4 (c6) 
lane 5: 6 (20) 9a (a7) 81 (81) 9b (9d) 
lane 6: 5 (20) ad (bb) 99 (99) b4 (b4) 
lane 7: 5 (20) ad (bb) 8b (8b) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 6 (20) 92 (9f) 6c (6c) 83 (83) 
lane 1: 7 (20) 89 (95) 64 (64) 79 (7c) 
lane 2: 8 (20) 9e (a9) 7a (7a) 92 (92) 
lane 3: 5 (20) 7a (88) 55 (55) 6e (6f) 
lane 4: 5 (20) e1 (ef) b8 (b8) d1 (d2) 
lane 5: 5 (20) be (cc) 85 (85) 9f (a1) 
lane 6: 6 (20) d0 (dd) a1 (a1) b9 (b8) 
lane 7: 6 (20) cf (dc) 92 (92) a9 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 6 (20) 96 (a3) 6c (6c) 82 (82) 
lane 1: 7 (20) 89 (95) 65 (65) 7c (7c) 
lane 2: 8 (20) a1 (ac) 7b (7b) 94 (94) 
lane 3: 5 (20) 78 (86) 59 (59) 71 (73) 
lane 4: 5 (20) e1 (ef) b8 (b8) d1 (d1) 
lane 5: 5 (20) bf (cd) 89 (89) a2 (a3) 
lane 6: 6 (20) d0 (dd) a2 (a2) ba (ba) 
lane 7: 6 (20) d0 (dd) 95 (95) ad (ac) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 0 (0)
[10b] = 1 (0)
CBMEM: root @ bf7ff000 254 entries.
[6dc] = 23faff
[6e8] = 23faff
Relocate MRC DATA from ff7ff128 to bf7ec000 (1472 bytes)
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : uKernel Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Unknown 0x00
Trying CBFS ramstage loader.
CBFS: loading stage fallback/ramstage @ 0x100000 (405564 bytes), entry @ 0x100000
EHCI debug port found in CBMEM.
coreboot-4.0-6755-g8128a56 Sat Sep  6 13:18:41 CEST 2014 booting...
clocks_per_usec: 2394
CBMEM: recovering 6/254 entries from root @ bf7ff000
Moving GDT to bf7ea000...ok
BS: BS_PRE_DEVICE times (us): entry 3007 run 0 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 0
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PNP: 00ff.1: enabled 1
PNP: 00ff.2: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 164e.3: enabled 1
PNP: 164e.2: enabled 0
PNP: 164e.7: enabled 0
PNP: 164e.19: enabled 0
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Compare with tree...
Root Device: enabled 1
 PNP: 00ff.1: enabled 1
 PNP: 00ff.2: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:16.2: enabled 1
  PCI: 00:19.0: enabled 1
  PCI: 00:1a.0: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 1
  PCI: 00:1c.1: enabled 1
  PCI: 00:1c.3: enabled 1
  PCI: 00:1c.4: enabled 1
  PCI: 00:1d.0: enabled 1
  PCI: 00:1f.0: enabled 1
   PNP: 164e.3: enabled 1
   PNP: 164e.2: enabled 0
   PNP: 164e.7: enabled 0
   PNP: 164e.19: enabled 0
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
   I2C: 00:54: enabled 1
   I2C: 00:55: enabled 1
   I2C: 00:56: enabled 1
   I2C: 00:57: enabled 1
   I2C: 00:5c: enabled 1
   I2C: 00:5d: enabled 1
   I2C: 00:5e: enabled 1
   I2C: 00:5f: enabled 1
 ... pmbase = 0x0500
scan_static_bus for Root Device
PNP: 00ff.1 enabled
recv_ec_data: 0x36
recv_ec_data: 0x51
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x30
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x12
recv_ec_data: 0x03
recv_ec_data: 0x10
recv_ec_data: 0x11
EC Firmware ID 6QHT30WW-3.18, Version 1.01B
recv_ec_data: 0x00
recv_ec_data: 0x10
recv_ec_data: 0x20
recv_ec_data: 0x30
recv_ec_data: 0x00
recv_ec_data: 0xa6
recv_ec_data: 0x01
recv_ec_data: 0x70
dock is not connected
PNP: 00ff.2 enabled
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0044] ops
Normal boot.
PCI: 00:00.0 [8086/0044] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0045] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0046] enabled
PCI: 00:16.0 [8086/0000] bus ops
PCI: 00:16.0 [8086/3b64] enabled
PCI: Static device PCI: 00:16.2 not found, disabling it.
PCI: 00:19.0 [8086/10ea] enabled
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/3b3c] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/3b56] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.0 subordinate bus PCI Express
PCI: 00:1c.0 [8086/3b42] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.1 subordinate bus PCI Express
PCI: 00:1c.1 [8086/3b44] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.3 subordinate bus PCI Express
PCI: 00:1c.3 [8086/3b48] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.4 subordinate bus PCI Express
PCI: 00:1c.4 [8086/3b4a] enabled
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/3b34] enabled
PCI: 00:1e.0 [8086/2448] bus ops
PCI: 00:1e.0 [8086/2448] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/3b07] enabled
PCI: 00:1f.2 [8086/0000] ops
PCI: 00:1f.2 [8086/3b2e] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/3b30] enabled
PCI: 00:1f.6 [8086/0000] ops
PCI: 00:1f.6 [8086/3b32] enabled
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:16.0
scan_static_bus for PCI: 00:16.0 done
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:1c.1
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 00:1c.3
PCI: pci_scan_bus for bus 04
PCI: pci_scan_bus returning with max=004
do_pci_scan_bridge returns max 4
do_pci_scan_bridge for PCI: 00:1c.4
PCI: pci_scan_bus for bus 05
PCI: 05:00.0 [168c/002e] enabled
PCI: pci_scan_bus returning with max=005
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x60
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
do_pci_scan_bridge returns max 5
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 06
PCI: pci_scan_bus returning with max=006
do_pci_scan_bridge returns max 6
scan_static_bus for PCI: 00:1f.0
PNP: 164e.3 enabled
PNP: 164e.2 disabled
PNP: 164e.7 disabled
PNP: 164e.19 disabled
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=006
scan_static_bus for Root Device done
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 225623 exit 0
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
ram_before_4g_top: 0xbf800000
TOUUD: 0x1340
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:1a.0 EHCI BAR hook registered
PCI: 00:1c.0 read_resources bus 2 link: 0
PCI: 00:1c.0 read_resources bus 2 link: 0 done
PCI: 00:1c.1 read_resources bus 3 link: 0
PCI: 00:1c.1 read_resources bus 3 link: 0 done
PCI: 00:1c.3 read_resources bus 4 link: 0
PCI: 00:1c.3 read_resources bus 4 link: 0 done
PCI: 00:1c.4 read_resources bus 5 link: 0
PCI: 00:1c.4 read_resources bus 5 link: 0 done
More than one caller of pci_ehci_read_resources from PCI: 00:1d.0
PCI: 00:1e.0 read_resources bus 6 link: 0
PCI: 00:1e.0 read_resources bus 6 link: 0 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI: 00:1f.3 read_resources bus 1 link: 0
PCI: 00:1f.3 read_resources bus 1 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 PNP: 00ff.1
  PNP: 00ff.1
  PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
  PNP: 00ff.2
  PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
  PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
  PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
  PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base c0000 size bf740000 align 0 gran 0 limit 0 flags e0004200 index 4
   PCI: 00:00.0 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
   PCI: 00:00.0 resource base c1c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 6
   PCI: 00:00.0 resource base c2000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0 resource base 100000000 size 34000000 align 0 gran 0 limit 0 flags e0004200 index 8
   PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index a
   PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index b
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
   PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
   PCI: 00:16.2
   PCI: 00:19.0
   PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
   PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
   PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1c.1
   PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1c.3
   PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1c.4 child on link 0 PCI: 05:00.0
   PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 05:00.0
    PCI: 05:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0
   PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1f.0 child on link 0 PNP: 164e.3
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
   PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
   PCI: 00:1f.0 resource base 1680 size 1c align 0 gran 0 limit 0 flags c0040100 index 10000400
    PNP: 164e.3
    PNP: 164e.3 resource base 200 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 164e.3 resource base b0 size 0 align 0 gran 0 limit 0 flags c0000400 index 29
    PNP: 164e.3 resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 164e.3 resource base 82 size 0 align 0 gran 0 limit 0 flags c0000400 index f0
    PNP: 164e.2
    PNP: 164e.2 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
    PNP: 164e.7
    PNP: 164e.7 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60
    PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 164e.19
    PNP: 164e.19 resource base 0 size 2 align 1 gran 1 limit ffff flags 100 index 60
    PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3 child on link 0 I2C: 01:54
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
    I2C: 01:54
    I2C: 01:55
    I2C: 01:56
    I2C: 01:57
    I2C: 01:5c
    I2C: 01:5d
    I2C: 01:5e
    I2C: 01:5f
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:19.0 18 *  [0x0 - 0x1f] io
PCI: 00:1f.2 20 *  [0x20 - 0x3f] io
PCI: 00:02.0 20 *  [0x40 - 0x47] io
PCI: 00:1f.2 10 *  [0x48 - 0x4f] io
PCI: 00:1f.2 18 *  [0x50 - 0x57] io
PCI: 00:1f.2 14 *  [0x58 - 0x5b] io
PCI: 00:1f.2 1c *  [0x5c - 0x5f] io
DOMAIN: 0000 compute_resources_io: base: 60 size: 60 align: 5 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 05:00.0 10 *  [0x0 - 0xffff] mem
PCI: 00:1c.4 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 10 *  [0x0 - 0x3fffff] mem
PCI: 00:1c.4 20 *  [0x400000 - 0x4fffff] mem
PCI: 00:19.0 10 *  [0x500000 - 0x51ffff] mem
PCI: 00:1b.0 10 *  [0x520000 - 0x523fff] mem
PCI: 00:19.0 14 *  [0x524000 - 0x524fff] mem
PCI: 00:1f.6 10 *  [0x525000 - 0x525fff] mem
PCI: 00:1f.2 24 *  [0x526000 - 0x5267ff] mem
PCI: 00:1a.0 10 *  [0x526800 - 0x526bff] mem
PCI: 00:1d.0 10 *  [0x526c00 - 0x526fff] mem
PCI: 00:1f.3 10 *  [0x527000 - 0x5270ff] mem
PCI: 00:16.0 10 *  [0x527100 - 0x52710f] mem
DOMAIN: 0000 compute_resources_mem: base: 527110 size: 527110 align: 22 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:19.0
constrain_resources: PCI: 00:1a.0
constrain_resources: PCI: 00:1b.0
constrain_resources: PCI: 00:1c.0
constrain_resources: PCI: 00:1c.1
constrain_resources: PCI: 00:1c.3
constrain_resources: PCI: 00:1c.4
constrain_resources: PCI: 05:00.0
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1e.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PNP: 164e.3
skipping PNP: 164e.3@29 fixed resource, size=0!
skipping PNP: 164e.3@f0 fixed resource, size=0!
constrain_resources: PCI: 00:1f.2
constrain_resources: PCI: 00:1f.3
constrain_resources: I2C: 01:54
constrain_resources: I2C: 01:55
constrain_resources: I2C: 01:56
constrain_resources: I2C: 01:57
constrain_resources: I2C: 01:5c
constrain_resources: I2C: 01:5d
constrain_resources: I2C: 01:5e
constrain_resources: I2C: 01:5f
constrain_resources: PCI: 00:1f.6
avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 0000169c lim->limit 0000ffff
avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
	lim->base c4000000 lim->limit cfffffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:169c size:60 align:5 gran:0 limit:ffff
Assigned: PCI: 00:19.0 18 *  [0x1800 - 0x181f] io
Assigned: PCI: 00:1f.2 20 *  [0x1820 - 0x183f] io
Assigned: PCI: 00:02.0 20 *  [0x1840 - 0x1847] io
Assigned: PCI: 00:1f.2 10 *  [0x1848 - 0x184f] io
Assigned: PCI: 00:1f.2 18 *  [0x1850 - 0x1857] io
Assigned: PCI: 00:1f.2 14 *  [0x1858 - 0x185b] io
Assigned: PCI: 00:1f.2 1c *  [0x185c - 0x185f] io
DOMAIN: 0000 allocate_resources_io: next_base: 1860 size: 60 align: 5 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
DOMAIN: 0000 allocate_resources_mem: base:cf800000 size:527110 align:22 gran:0 limit:cfffffff
Assigned: PCI: 00:02.0 10 *  [0xcf800000 - 0xcfbfffff] mem
Assigned: PCI: 00:1c.4 20 *  [0xcfc00000 - 0xcfcfffff] mem
Assigned: PCI: 00:19.0 10 *  [0xcfd00000 - 0xcfd1ffff] mem
Assigned: PCI: 00:1b.0 10 *  [0xcfd20000 - 0xcfd23fff] mem
Assigned: PCI: 00:19.0 14 *  [0xcfd24000 - 0xcfd24fff] mem
Assigned: PCI: 00:1f.6 10 *  [0xcfd25000 - 0xcfd25fff] mem
Assigned: PCI: 00:1f.2 24 *  [0xcfd26000 - 0xcfd267ff] mem
Assigned: PCI: 00:1a.0 10 *  [0xcfd26800 - 0xcfd26bff] mem
Assigned: PCI: 00:1d.0 10 *  [0xcfd26c00 - 0xcfd26fff] mem
Assigned: PCI: 00:1f.3 10 *  [0xcfd27000 - 0xcfd270ff] mem
Assigned: PCI: 00:16.0 10 *  [0xcfd27100 - 0xcfd2710f] mem
DOMAIN: 0000 allocate_resources_mem: next_base: cfd27110 size: 527110 align: 22 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:01.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.1 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.1 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.3 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.3 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.4 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.4 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.4 allocate_resources_mem: base:cfc00000 size:100000 align:20 gran:20 limit:cfffffff
Assigned: PCI: 05:00.0 10 *  [0xcfc00000 - 0xcfc0ffff] mem
PCI: 00:1c.4 allocate_resources_mem: next_base: cfc10000 size: 100000 align: 20 gran: 20 done
PCI: 00:1e.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1e.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1e.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1e.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:02.0 10 <- [0x00cf800000 - 0x00cfbfffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 20 <- [0x0000001840 - 0x0000001847] size 0x00000008 gran 0x03 io
PCI: 00:16.0 10 <- [0x00cfd27100 - 0x00cfd2710f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00cfd00000 - 0x00cfd1ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00cfd24000 - 0x00cfd24fff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000001800 - 0x000000181f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 EHCI Debug Port hook triggered
PCI: 00:1a.0 10 <- [0x00cfd26800 - 0x00cfd26bff] size 0x00000400 gran 0x0a mem
PCI: 00:1a.0 EHCI Debug Port relocated
PCI: 00:1b.0 10 <- [0x00cfd20000 - 0x00cfd23fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.1 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.1 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:1c.3 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:1c.3 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 04 mem
PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:1c.4 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:1c.4 20 <- [0x00cfc00000 - 0x00cfcfffff] size 0x00100000 gran 0x14 bus 05 mem
PCI: 00:1c.4 assign_resources, bus 5 link: 0
PCI: 05:00.0 10 <- [0x00cfc00000 - 0x00cfc0ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:1c.4 assign_resources, bus 5 link: 0
PCI: 00:1d.0 10 <- [0x00cfd26c00 - 0x00cfd26fff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io
PCI: 00:1e.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 06 prefmem
PCI: 00:1e.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 06 mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 164e.3 60 <- [0x0000000200 - 0x0000000207] size 0x00000008 gran 0x03 io
PNP: 164e.3 29 <- [0x00000000b0 - 0x00000000af] size 0x00000000 gran 0x00 irq
PNP: 164e.3 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
PNP: 164e.3 f0 <- [0x0000000082 - 0x0000000081] size 0x00000000 gran 0x00 irq
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000001848 - 0x000000184f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000001858 - 0x000000185b] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000001850 - 0x0000001857] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x000000185c - 0x000000185f] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000001820 - 0x000000183f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00cfd26000 - 0x00cfd267ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00cfd27000 - 0x00cfd270ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.6 10 <- [0x00cfd25000 - 0x00cfd25fff] size 0x00001000 gran 0x0c mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 PNP: 00ff.1
  PNP: 00ff.1
  PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
  PNP: 00ff.2
  PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
  PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
  PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
  PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 169c size 60 align 5 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base cf800000 size 527110 align 22 gran 0 limit cfffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base c0000 size bf740000 align 0 gran 0 limit 0 flags e0004200 index 4
   PCI: 00:00.0 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
   PCI: 00:00.0 resource base c1c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 6
   PCI: 00:00.0 resource base c2000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0 resource base 100000000 size 34000000 align 0 gran 0 limit 0 flags e0004200 index 8
   PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index a
   PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index b
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
   PCI: 00:01.0
   PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:01.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:01.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:02.0
   PCI: 00:02.0 resource base cf800000 size 400000 align 22 gran 22 limit cfffffff flags 60000201 index 10
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
   PCI: 00:02.0 resource base 1840 size 8 align 3 gran 3 limit ffff flags 60000100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base cfd27100 size 10 align 4 gran 4 limit cfffffff flags 60000201 index 10
   PCI: 00:16.2
   PCI: 00:19.0
   PCI: 00:19.0 resource base cfd00000 size 20000 align 17 gran 17 limit cfffffff flags 60000200 index 10
   PCI: 00:19.0 resource base cfd24000 size 1000 align 12 gran 12 limit cfffffff flags 60000200 index 14
   PCI: 00:19.0 resource base 1800 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base cfd26800 size 400 align 10 gran 10 limit cfffffff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base cfd20000 size 4000 align 14 gran 14 limit cfffffff flags 60000201 index 10
   PCI: 00:1c.0
   PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1c.1
   PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.1 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.1 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1c.3
   PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.3 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.3 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1c.4 child on link 0 PCI: 05:00.0
   PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.4 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.4 resource base cfc00000 size 100000 align 20 gran 20 limit cfffffff flags 60080202 index 20
    PCI: 05:00.0
    PCI: 05:00.0 resource base cfc00000 size 10000 align 16 gran 16 limit cfffffff flags 60000201 index 10
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base cfd26c00 size 400 align 10 gran 10 limit cfffffff flags 60000200 index 10
   PCI: 00:1e.0
   PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1e.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1e.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1f.0 child on link 0 PNP: 164e.3
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
   PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
   PCI: 00:1f.0 resource base 1680 size 1c align 0 gran 0 limit 0 flags c0040100 index 10000400
    PNP: 164e.3
    PNP: 164e.3 resource base 200 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 164e.3 resource base b0 size 0 align 0 gran 0 limit 0 flags e0000400 index 29
    PNP: 164e.3 resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 164e.3 resource base 82 size 0 align 0 gran 0 limit 0 flags e0000400 index f0
    PNP: 164e.2
    PNP: 164e.2 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75
    PNP: 164e.7
    PNP: 164e.7 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60
    PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 164e.19
    PNP: 164e.19 resource base 0 size 2 align 1 gran 1 limit ffff flags 100 index 60
    PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 1848 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:1f.2 resource base 1858 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:1f.2 resource base 1850 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:1f.2 resource base 185c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:1f.2 resource base 1820 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1f.2 resource base cfd26000 size 800 align 11 gran 11 limit cfffffff flags 60000200 index 24
   PCI: 00:1f.3 child on link 0 I2C: 01:54
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base cfd27000 size 100 align 8 gran 8 limit cfffffff flags 60000201 index 10
    I2C: 01:54
    I2C: 01:55
    I2C: 01:56
    I2C: 01:57
    I2C: 01:5c
    I2C: 01:5d
    I2C: 01:5e
    I2C: 01:5f
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base cfd25000 size 1000 align 12 gran 12 limit cfffffff flags 60000201 index 10
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 1051000 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 17aa/2193
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 00
PCI: 00:02.0 subsystem <- 17aa/215a
PCI: 00:02.0 cmd <- 03
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 17aa/2153
PCI: 00:19.0 cmd <- 03
PCI: 00:1a.0 subsystem <- 17aa/2163
PCI: 00:1a.0 cmd <- 02
PCI: 00:1b.0 subsystem <- 17aa/215e
PCI: 00:1b.0 cmd <- 02
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 cmd <- 00
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 cmd <- 00
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 cmd <- 00
PCI: 00:1c.4 bridge ctrl <- 0003
PCI: 00:1c.4 cmd <- 06
PCI: 00:1d.0 subsystem <- 17aa/2163
PCI: 00:1d.0 cmd <- 02
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 00 (NOT WRITTEN!)
pch_decode_init
PCI: 00:1f.0 subsystem <- 17aa/2166
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 17aa/2168
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 17aa/2167
PCI: 00:1f.3 cmd <- 03
PCI: 00:1f.6 cmd <- 02
PCI: 05:00.0 cmd <- 02
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 34749 exit 0
Initializing devices...
Root Device init
starting SPI configuration
SPI configured
Keyboard init...
Keyboard controller output buffer result timeout
Root Device init 516575 usecs
CPU_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Installing SMM handler to 0xbf800000
Installing IED header to 0xbfc00000
Initializing SMM handler... ... pmbase = 0x0500

SMI_STS: MCSMI PM1 
PM1_STS: WAK BM TMROF 
GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
TCO_STS: 
  ... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 20655
CPU: family 06, model 25, stepping 05
Enabling cache
CBFS: WARNING: 'cpu_microcode_blob.bin' not found.
CPU: Intel(R) Core(TM) i3 CPU       M 370  @ 2.40GHz.
CPU:lapic=0, boot_cpu=1
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6
0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x0000000134000000 size 0x34000000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
MTRR: default type WB/UC MTRR counts: 4/5.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
Enabling VMX
model_x06ax: frequency set to 2394
Turbo is unavailable
CPU: 0 has 2 cores, 2 threads per core
CPU: 0 has core 1
CPU1: stack_base 0015d000, stack_end 0015dff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
CPU: vendor Intel device 20655
Waiting for send to finish...
CPU: family 06, model 25, stepping 05
+Enabling cache
Sending STARTUP #2 to 1.
CBFS: WARNING: 'cpu_microcode_blob.bin' not found.
After apic_write.
CPU: Intel(R) Core(TM) i3 CPU       M 370  @ 2.40GHz.
Startup point 1.
Waiting for send to finish...
+CPU:lapic=1, boot_cpu=0
After Startup.
MTRR: Fixed MSR 0x250 0x0606060606060606
CPU: 0 has core 4
MTRR: Fixed MSR 0x258 0x0606060606060606
CPU2: stack_base 0015c000, stack_end 0015cff8
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
Asserting INIT.
MTRR: Fixed MSR 0x26a 0x0606060606060606
Waiting for send to finish...
MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
Deasserting INIT.
MTRR: Fixed MSR 0x26d 0x0606060606060606
Waiting for send to finish...
MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
#startup loops: 2.
call enable_fixed_mtrr()
Sending STARTUP #1 to 4.
MTRR: 0 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
After apic_write.
MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
Startup point 1.
Initializing CPU #2
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
CPU: vendor Intel device 20655
Waiting for send to finish...
CPU: family 06, model 25, stepping 05
+Enabling cache
MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
CBFS: WARNING: 'cpu_microcode_blob.bin' not found.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Sending STARTUP #2 to 4.
After apic_write.
Setting up local apic...Startup point 1.
Waiting for send to finish...
+ apic_id: 0x01 done.
Enabling VMX
After Startup.
model_x06ax: frequency set to 2394
CPU: 0 has core 5
CPU3: stack_base 0015b000, stack_end 0015bff8
CPU #1 initialized
Asserting INIT.
Waiting for send to finish...
+CPU: Intel(R) Core(TM) i3 CPU       M 370  @ 2.40GHz.
Deasserting INIT.
Waiting for send to finish...
+CPU:lapic=4, boot_cpu=0
#startup loops: 2.
Sending STARTUP #1 to 5.
After apic_write.
MTRR: Fixed MSR 0x250 0x0606060606060606
Startup point 1.
Waiting for send to finish...
+MTRR: Fixed MSR 0x258 0x0606060606060606
Sending STARTUP #2 to 5.
After apic_write.
MTRR: Fixed MSR 0x259 0x0000000000000000
Startup point 1.
Waiting for send to finish...
+MTRR: Fixed MSR 0x268 0x0606060606060606
After Startup.
CPU #0 initialized
Waiting for 2 CPUS to stop
Initializing CPU #3
MTRR: Fixed MSR 0x269 0x0606060606060606
CPU: vendor Intel device 20655
MTRR: Fixed MSR 0x26a 0x0606060606060606
CPU: family 06, model 25, stepping 05
MTRR: Fixed MSR 0x26b 0x0606060606060606
Enabling cache
MTRR: Fixed MSR 0x26c 0x0606060606060606
CBFS: WARNING: 'cpu_microcode_blob.bin' not found.
MTRR: Fixed MSR 0x26d 0x0606060606060606
CPU: Intel(R) Core(TM) i3 CPU       M 370  @ 2.40GHz.
MTRR: Fixed MSR 0x26e 0x0606060606060606
CPU:lapic=5, boot_cpu=0
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
call enable_fixed_mtrr()
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: 0 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
MTRR: Fixed MSR 0x26a 0x0606060606060606

MTRR check
MTRR: Fixed MSR 0x26b 0x0606060606060606
Fixed MTRRs   : MTRR: Fixed MSR 0x26c 0x0606060606060606
Enabled
MTRR: Fixed MSR 0x26d 0x0606060606060606
Variable MTRRs: MTRR: Fixed MSR 0x26e 0x0606060606060606
Enabled
MTRR: Fixed MSR 0x26f 0x0606060606060606

call enable_fixed_mtrr()
Setting up local apic...MTRR: 0 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
 apic_id: 0x04 MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
done.
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
Enabling VMX
MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
model_x06ax: frequency set to 2394

MTRR check
CPU #2 initialized
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled
Waiting for 1 CPUS to stop

Setting up local apic... apic_id: 0x05 done.
Enabling VMX
model_x06ax: frequency set to 2394
CPU #3 initialized
All AP CPUs stopped (16190 loops)
CPU1: stack: 0015d000 - 0015e000, lowest used address 0015dc94, stack used: 876 bytes
CPU2: stack: 0015c000 - 0015d000, lowest used address 0015cc94, stack used: 876 bytes
CPU3: stack: 0015b000 - 0015c000, lowest used address 0015bc94, stack used: 876 bytes
CPU_CLUSTER: 0 init 464125 usecs
PCI: 00:00.0 init
Set BIOS_RESET_CPL
PCI: 00:00.0 init 2500 usecs
PCI: 00:02.0 init
GT Power Management Init
IVB GT1 Power Meter Weights
GT init timeout
Initializing VGA without OPROM. MMIO 0xcf800000
EDID:
00 ff ff ff ff ff ff 00 30 ae 11 40 00 00 00 00 
00 13 01 03 80 1a 10 78 ea 5c d5 93 5c 5e 8e 27 
1c 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 
01 01 01 01 01 01 ee 1a 00 80 50 20 10 30 10 30 
13 00 05 a3 10 00 00 19 d0 17 00 c6 50 20 19 30 
30 20 36 00 05 a3 10 00 00 19 00 00 00 0f 00 81 
0a 3c 81 0a 32 16 09 00 4c a3 41 54 00 00 00 fe 
00 4c 54 4e 31 32 31 41 54 30 37 4c 30 32 00 38 
Extracted contents:
header:          00 ff ff ff ff ff ff 00
serial number:   30 ae 11 40 00 00 00 00 00 13
version:         01 03
basic params:    80 1a 10 78 ea
chroma info:     5c d5 93 5c 5e 8e 27 1c 50 54
established:     00 00 00
standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1:    ee 1a 00 80 50 20 10 30 10 30 13 00 05 a3 10 00 00 19
descriptor 2:    d0 17 00 c6 50 20 19 30 30 20 36 00 05 a3 10 00 00 19
descriptor 3:    00 00 00 0f 00 81 0a 3c 81 0a 32 16 09 00 4c a3 41 54
descriptor 4:    00 00 00 fe 00 4c 54 4e 31 32 31 41 54 30 37 4c 30 32
extensions:      00
checksum:        38

Manufacturer: LEN Model 4011 Serial Number 0
Made week 0 of 2009
EDID version: 1.3
Digital display
Maximum image size: 26 cm x 16 cm
Gamma: 220%
Check DPMS levels
DPMS levels: Standby Suspend Off
Supported color formats: RGB 4:4:4, YCrCb 4:2:2
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: ee1a0080502010301030130005a310000019
Did detailed timing
Detailed mode (IN HEX): Clock 68940 KHz, 105 mm x a3 mm
               0500 0510 0540 0580 hborder 0
               0320 0321 0324 0330 vborder 0
               -hsync -vsync 
Hex of detail: d01700c6502019303020360005a310000019
Detailed mode (IN HEX): Clock 68940 KHz, 105 mm x a3 mm
               0500 0510 0540 0580 hborder 0
               0320 0321 0324 0330 vborder 0
               -hsync -vsync 
Hex of detail: 0000000f00810a3c810a321609004ca34154
Manufacturer-specified data, tag 15
Hex of detail: 000000fe004c544e313231415430374c3032
ASCII string: LTN121AT07L02
Checksum
Checksum: 0x38 (valid)

Unknown extension block

EDID block does NOT conform to EDID 1.3!
	Missing name descriptor
	Missing monitor ranges
EDID block does not conform at all!
	Detailed blocks filled with garbage
bringing up panel at resolution 1280 x 800
Borders 0 x 0
Blank 128 x 16
Sync 48 x 3
Front porch 16 x 1
Spread spectrum clock
Single channel
Polarities 1, 1
Data M1=1204813, N1=8388608
Link frequency 270000 kHz
Link M1=133868, N1=524288
Pixel N=8, M1=24, M2=9, P1=2
Pixel clock 138214 kHz
waiting for panel powerup
panel powered up
GT Power Management Init (post VBIOS)
GT init timeout
PCI: 00:02.0 init 220628 usecs
PCI: 00:16.0 init
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : YES
ME: Manufacturing Mode      : YES
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Host communication established
ME: BIOS path: Normal
ME: Extend SHA-256: 4525e6abe84786a34336e0a901dcaacbfc97cfc5bf640f7b78eb11bac53c2f86
PCI: 00:16.0 init 23001 usecs
PCI: 00:19.0 init
PCI: 00:19.0 init 749 usecs
PCI: 00:1a.0 init
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init 1999 usecs
PCI: 00:1b.0 init
Azalia: base = cfd20000
Azalia: V1CTL disabled.
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862804
Azalia: verb_size: 16
Azalia: verb loaded.
Azalia: Initializing codec #0
Azalia: codec viddid: 14f15069
Azalia: verb_size: 44
Azalia: verb loaded.
PCI: 00:1b.0 init 15126 usecs
PCI: 00:1d.0 init
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init 1999 usecs
PCI: 00:1e.0 init
PCI init.
PCI: 00:1e.0 init 1259 usecs
PCI: 00:1f.0 init
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x01
IOAPIC: Dumping registers
  reg 0x0000: 0x01000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
Set power off after power failure.
NMI sources disabled.
Mobile 5 PM init
rtc_failed = 0x0
RTC Init
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
Locking SMM.
PCI: 00:1f.0 init 16252 usecs
PCI: 00:1f.2 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: CFD26000
PCI: 00:1f.2 init 3031 usecs
PCI: 00:1f.3 init
PCI: 00:1f.3 init 755 usecs
PCI: 00:1f.6 init
Thermal init start.
Thermal init done.
PCI: 00:1f.6 init 2250 usecs
PCI: 05:00.0 init
PCI: 05:00.0 init 750 usecs
PNP: 164e.3 init
PNP: 164e.3 init 750 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
I2C: 01:54 init 1500 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
I2C: 01:55 init 1499 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
I2C: 01:56 init 1499 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
I2C: 01:57 init 1500 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init 28499 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
I2C: 01:5d init 1500 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
I2C: 01:5e init 1499 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
I2C: 01:5f init 1499 usecs
Devices initialized
Show all devs...After init.
Root Device: enabled 1
PNP: 00ff.1: enabled 1
PNP: 00ff.2: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.2: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 164e.3: enabled 1
PNP: 164e.2: enabled 0
PNP: 164e.7: enabled 0
PNP: 164e.19: enabled 0
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:5c: enabled 1
I2C: 01:5d: enabled 1
I2C: 01:5e: enabled 1
I2C: 01:5f: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1f.6: enabled 1
PCI: 05:00.0: enabled 1
APIC: 01: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 1373099 exit 0
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 1497 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
Updating MRC cache data.
find_current_mrc_cache_local: picked entry 1 from cache block
SF: Detected MX25L6405D with page size 1000, total 800000
find_next_mrc_cache: picked next entry from cache block at fffe2000
Finally: write MRC cache update to flash at fffe2000
Copying Interrupt Routing Table to 0x000f0000... done.
Copying Interrupt Routing Table to 0xbf7e9000... done.
PIRQ table: 288 bytes.
Wrote the mp table end at: 000f0410 - 000f05dc
Wrote the mp table end at: bf7e8010 - bf7e81dc
MP table: 476 bytes.
ACPI: Writing ACPI tables at bf7dc000.
ACPI:    * HPET
ACPI: added table 1/32, length now 40
ACPI:    * MADT
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:     * FACS
ACPI: Patching up global NVS in DSDT at offset 0x020d -> 0xbf7dfea0
ACPI:     * DSDT @ bf7dc360 Length 3b31
ACPI:     * FADT
ACPI: added table 4/32, length now 52
ACPI:     * SSDT
Found 1 CPU(s) with 4 core(s) each.
PSS: 2400MHz power 25000 control 0x12 status 0x12
PSS: 2266MHz power 23316 control 0x11 status 0x11
PSS: 2133MHz power 21689 control 0x10 status 0x10
PSS: 2000MHz power 20116 control 0xf status 0xf
PSS: 1866MHz power 18531 control 0xe status 0xe
PSS: 1733MHz power 17021 control 0xd status 0xd
PSS: 1600MHz power 15517 control 0xc status 0xc
PSS: 1466MHz power 14068 control 0xb status 0xb
PSS: 1333MHz power 12640 control 0xa status 0xa
PSS: 1200MHz power 11250 control 0x9 status 0x9
PSS: 1066MHz power 9867 control 0x8 status 0x8
PSS: 933MHz power 8516 control 0x7 status 0x7
PSS: 2400MHz power 25000 control 0x12 status 0x12
PSS: 2266MHz power 23316 control 0x11 status 0x11
PSS: 2133MHz power 21689 control 0x10 status 0x10
PSS: 2000MHz power 20116 control 0xf status 0xf
PSS: 1866MHz power 18531 control 0xe status 0xe
PSS: 1733MHz power 17021 control 0xd status 0xd
PSS: 1600MHz power 15517 control 0xc status 0xc
PSS: 1466MHz power 14068 control 0xb status 0xb
PSS: 1333MHz power 12640 control 0xa status 0xa
PSS: 1200MHz power 11250 control 0x9 status 0x9
PSS: 1066MHz power 9867 control 0x8 status 0x8
PSS: 933MHz power 8516 control 0x7 status 0x7
PSS: 2400MHz power 25000 control 0x12 status 0x12
PSS: 2266MHz power 23316 control 0x11 status 0x11
PSS: 2133MHz power 21689 control 0x10 status 0x10
PSS: 2000MHz power 20116 control 0xf status 0xf
PSS: 1866MHz power 18531 control 0xe status 0xe
PSS: 1733MHz power 17021 control 0xd status 0xd
PSS: 1600MHz power 15517 control 0xc status 0xc
PSS: 1466MHz power 14068 control 0xb status 0xb
PSS: 1333MHz power 12640 control 0xa status 0xa
PSS: 1200MHz power 11250 control 0x9 status 0x9
PSS: 1066MHz power 9867 control 0x8 status 0x8
PSS: 933MHz power 8516 control 0x7 status 0x7
PSS: 2400MHz power 25000 control 0x12 status 0x12
PSS: 2266MHz power 23316 control 0x11 status 0x11
PSS: 2133MHz power 21689 control 0x10 status 0x10
PSS: 2000MHz power 20116 control 0xf status 0xf
PSS: 1866MHz power 18531 control 0xe status 0xe
PSS: 1733MHz power 17021 control 0xd status 0xd
PSS: 1600MHz power 15517 control 0xc status 0xc
PSS: 1466MHz power 14068 control 0xb status 0xb
PSS: 1333MHz power 12640 control 0xa status 0xa
PSS: 1200MHz power 11250 control 0x9 status 0x9
PSS: 1066MHz power 9867 control 0x8 status 0x8
PSS: 933MHz power 8516 control 0x7 status 0x7
Digitizer state forced as absent
ACPI: added table 5/32, length now 56
current = bf7e0e80
ACPI: done.
Laptop handling...
ACPI tables: 20096 bytes.
smbios_write_tables: bf7db000
Root Device (LENOVO 3626EN1)
recv_ec_data: 0x36
recv_ec_data: 0x51
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x30
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x12
recv_ec_data: 0x03
PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
PNP: 00ff.2 (Lenovo H8 EC)
CPU_CLUSTER: 0 (Intel i7 (Nehalem) integrated Northbridge)
APIC: 00 (Intel Nehalem CPU)
DOMAIN: 0000 (Intel i7 (Nehalem) integrated Northbridge)
PCI: 00:00.0 (Intel i7 (Nehalem) integrated Northbridge)
PCI: 00:02.0 (Intel i7 (Nehalem) integrated Northbridge)
PCI: 00:16.2 (unknown)
PCI: 00:19.0 (unknown)
PCI: 00:1a.0 (unknown)
PCI: 00:1b.0 (unknown)
PCI: 00:1c.0 (unknown)
PCI: 00:1c.1 (unknown)
PCI: 00:1c.3 (unknown)
PCI: 00:1c.4 (unknown)
PCI: 00:1d.0 (unknown)
PCI: 00:1f.0 (unknown)
PNP: 164e.3 (NSC PC87382 Docking LPC Switch)
PNP: 164e.2 (NSC PC87382 Docking LPC Switch)
PNP: 164e.7 (NSC PC87382 Docking LPC Switch)
PNP: 164e.19 (NSC PC87382 Docking LPC Switch)
PCI: 00:1f.2 (unknown)
PCI: 00:1f.3 (unknown)
I2C: 01:54 (AT24RF08C)
I2C: 01:55 (AT24RF08C)
I2C: 01:56 (AT24RF08C)
I2C: 01:57 (AT24RF08C)
I2C: 01:5c (AT24RF08C)
I2C: 01:5d (AT24RF08C)
I2C: 01:5e (AT24RF08C)
I2C: 01:5f (AT24RF08C)
PCI: 00:01.0 (unknown)
PCI: 00:16.0 (unknown)
PCI: 00:1e.0 (unknown)
PCI: 00:1f.6 (unknown)
PCI: 05:00.0 (unknown)
APIC: 01 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
SMBIOS tables: 424 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 1071
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0xbf6d3000
rom_table_end = 0xbf6d3000
... aligned to 0xbf6e0000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-00000000bf6d2fff: RAM
 4. 00000000bf6d3000-00000000bf7fffff: CONFIGURATION TABLES
 5. 00000000bf800000-00000000bfffffff: RESERVED
 6. 00000000c1c00000-00000000c3ffffff: RESERVED
 7. 00000000d0000000-00000000efffffff: RESERVED
 8. 00000000fed00000-00000000fedfffff: RESERVED
 9. 0000000100000000-0000000133ffffff: RAM
Wrote coreboot table at: bf6d3000, 0x1c4 bytes, checksum bf03
coreboot table: 476 bytes.
CBMEM ROOT  0. bf7ff000 00001000
CAR GLOBALS 1. bf7fe000 00001000
USBDEBUG    2. bf7fd000 00001000
CONSOLE     3. bf7ed000 00010000
MRC DATA    4. bf7ec000 00001000
ROMSTAGE    5. bf7eb000 00001000
GDT         6. bf7ea000 00001000
IRQ TABLE   7. bf7e9000 00001000
SMP TABLE   8. bf7e8000 00001000
ACPI        9. bf7dc000 0000c000
SMBIOS     10. bf7db000 00001000
ACPI RESUME11. bf6db000 00100000
COREBOOT   12. bf6d3000 00008000
BS: BS_WRITE_TABLES times (us): entry 18328 run 227409 exit 0
CBFS: located payload @ fff2ca78, 305146 bytes.
Loading segment from rom address 0xfff2ca78
  code (compression=1)
  New segment dstaddr 0x8200 memsize 0x17378 srcaddr 0xfff2cacc filesize 0x8230
  (cleaned up) New segment addr 0x8200 size 0x17378 offset 0xfff2cacc filesize 0x8230
Loading segment from rom address 0xfff2ca94
  code (compression=1)
  New segment dstaddr 0x100000 memsize 0xee11c srcaddr 0xfff34cfc filesize 0x42576
  (cleaned up) New segment addr 0x100000 size 0xee11c offset 0xfff34cfc filesize 0x42576
Loading segment from rom address 0xfff2cab0
  Entry Point 0x00008200
Bounce Buffer at bf581000, 1380696 bytes
Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017378 filesz: 0x0000000000008230
lb: [0x0000000000100000, 0x000000000016303c)
Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017378 filesz: 0x0000000000008230
using LZMA
[ 0x00008200, 00017c3f, 0x0001f578) <- fff2cacc
Clearing Segment: addr: 0x0000000000017c3f memsz: 0x0000000000007939
dest 00008200, end 0001f578, bouncebuffer bf581000
Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000ee11c filesz: 0x0000000000042576
lb: [0x0000000000100000, 0x000000000016303c)
segment: [0x0000000000100000, 0x0000000000142576, 0x00000000001ee11c)
 bounce: [0x00000000bf581000, 0x00000000bf5c3576, 0x00000000bf66f11c)
Post relocation: addr: 0x00000000bf581000 memsz: 0x00000000000ee11c filesz: 0x0000000000042576
using LZMA
[ 0xbf581000, bf66f11c, 0xbf66f11c) <- fff34cfc
dest bf581000, end bf66f11c, bouncebuffer bf581000
move suffix around: from bf5e403c, to 16303c, amount: 8b0e0
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 145749 exit 0
PCH watchdog disabled
Jumping to boot code at 00008200
CPU0: stack: 0015e000 - 0015f000, lowest used address 0015ea70, stack used: 1424 bytes
entry    = 0x00008200
lb_start = 0x00100000
lb_size  = 0x0006303c
buffer   = 0xbf581000
