On 09/17/14 21:26, Aaron Durbin wrote:
On Wed, Sep 17, 2014 at 4:29 AM, DM365 <[email protected]> wrote:
     I'm trying to investigate Coreboot and intel FSP in minnowmax board
,followed by
"http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372".‍‍

     But ,the uart log show :

     Payload being loaded below 1MiB without region being marked as RAM
usable.
     Could not find a bounce buffer...
     Could not load payload‍



Hi Aaron,

This happens if you make a ROM image without the IFD (Intel Flash Desciptor)
I had the same problem.

Ref: review.coreboot.org/#/c/5792/

We need to preserve the existing Intel Flash Descriptor & TXE binary.

Mohan


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