As I remember, Rangeley FSP is using UART1(0x2F8) as default, can you try to configure UART1 on your platform?
On Tue, Sep 16, 2014 at 11:50 PM, Qinqxin Wei <[email protected]> wrote: > Hi, > > I am managing to replace BIOS with coreboot on a Rangeley evaluation > board, but the serial console cannot display message after coreboot calls > console_init() in src/southbridge/intel/fsp_rangeley/romstage.c. > > The console is connected to UART0 (0x3f8), which has been verified by BIOS. > > My configuration of coreboot includes: > Mainboard: Intel->Mohon Peak CRB, which is the only choice for Rangeley > FSP and microcode: downloaded from Intel FSP ( > https://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=23676). > Payload: U-boot-x86 (should be irrelevant to payload, since coreboot just > enters romstage) > > I have checked that the UART0 registers should have been initialized. > The TX FIFO should also work: after out something to 0x3f8, LSR will > change. > I have also checked some other registers might related to UART. > The UART_CONT (0:1f.0-0x80) is in the default state (0x00000003). > The GPIO Use Select is also in default state: GPIOS_13 is 0. > > Is there any other register can block the UART output? > > Besides, actually the coreboot finally run deeply. > The post code changes from 47->66->67->69->...>72->73->77... and finally > stop at 0xE2. > But there's no console display so I cannot know where it stops. > > Regards, > Qingxin > > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot >
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