Hi Hook Guo, 2015-03-27 11:11 GMT+01:00 郭佳 <[email protected]>: > At the time this main function has been called, the Cache as RAM has been > setup > by FSP, and the MTRR_PHYSBASE0 is FEF0_0006.
> BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of > temporary stack are full of A5 5A, is it the correct case? For FSP related questions you should ask your Intel developer relations contact or sales representative. FSP isn't open source, and so we can't help you since we have no idea what it does either, and even if people knew, there also isn't a lot of interest within the coreboot community to provide free support for components like these. Thank you for your understanding, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
