Dear Matt, dear Duncan,
Am Donnerstag, den 09.04.2015, 18:11 -0500 schrieb Matt DeVillier: > On 4/9/2015 1:21 PM, Duncan Laurie wrote: > > [I got a bounce when sending this so trying again] > > > > I think you should be able to alter the behavior with the 0xf2 and 0xf4 > > registers in the LDN4 block. > > > > Right now mainboard/google/panther/devicetree.cb has this: > > > > device pnp 2e.4 on # Environment Controller > > io 0x60 = 0x700 > > io 0x62 = 0x710 > > irq 0x70 = 0x09 > > irq 0xf2 = 0x20 <<<<< PCR 1 > > irq 0xf4 = 0x0 <<<<< PCR 2 > > irq 0xfa = 0x12 > > end > > > > 0xf2 bit 5 and 0xf4 bit 5,6 should have some effect on this behavior. > > > > F4<5> and F2<5>: > > 1 X : Always ON > > 0 1 : Memory > > 0 0 : Always OFF > > > > And then F4<6> seems to be the bit that gates the PWRON pulse from the > > superio and lets the southbridge control the default behavior. > > > > I think if you set "irq 0xf2 = 0x20" (in theory if the datasheet is right > > F2<5> doesn't matter for always on) and "irq 0xf4 = 0x20" and then do not > > call it8772f_ac_resume_southbridge() (which is setting 0xf4=0x60) it should > > let the superio control the behavior and always power on when AC Is > > attached. > > that seems to have done the trick, thanks! I was misunderstanding the > functionality of F4<5>, appreciate the clarification Duncan, thank you for the analysis and solution. Matt, are you planning to write a proper change set to make this run-time configurable using the user option table (NVRAM)? That’d be great! […] Thanks, Paul
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