SPD is some data saved on the memory module, available to the processor to read to find out memory properies. These data are protected by a check code (CRC) which allows the CPU to verify that it read the data correctly. Apparently this check is failing in your case.
Some likely reasons could be a noisy i2c interface (used to read SPD) or someone writing the SPD storage on memory module(s) and corrupteding it. --vb On Wed, May 20, 2015 at 8:51 AM, Michael Gerlach <[email protected]> wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi all, > > i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like > there are some issues regarding the size of the modules.. > > http://pastebin.com/mLcS6vhQ > > Best regards, > > > n3ph > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v2 > > iQEcBAEBAgAGBQJVXK2LAAoJEE1l5S41evqaCa8IAMqXBkzXdd72Vsi4mJ6MT73e > V3SMLABBJZ/IdEtea1HixhaTYVgyhghMsNsw3rgPSugN0bPKCutL647xz8xORv2r > hHQWDO0VF4KScPtGH1cG6YgtZuVB+IJZusM2SqR5WRikGqAV3jn0q1EQbW2CFG4K > JzaqhVHUYta/iDi3utvT66CmlJuzr6A+PneB2NvrWc61inHzT8sLM/r55J6zyBH3 > 4IOw15wJTwPkogHrGeN5artKt7qeKgdUv8VrZZPWtO86qW8QroexQND5mlc+yqyq > IQBQ0uzm8FkBkI8WeYQvMCLnfd6iW57pGnxQysf+soDy8+1+/c7xAqkXp5nn3b8= > =QBlQ > -----END PGP SIGNATURE----- > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
