Dear Jonathan,
Am Freitag, den 25.03.2016, 04:38 +0100 schrieb Jonathan Neuschäfer: > Below is a link to my GSoC project proposal draft[1]. In essence it's > about porting coreboot to a non-emulated board with a RISC-V CPU. If you > have any comments, please go ahead and add them to the document. thank you very much for your promising proposal! > The exact RISC-V board is not yet decided, but I'll fix that as soon as > I can. What alternatives are there? > Also, I'm not sure about the timeline. It currently weighs heavily on > the first half. Maybe I'm not giving the individual subtasks enough > time; maybe I have not listed enough subtasks to fill the three months > time frame. Looking at it, I’d say, two weeks for implementing RAM initialization is a bit short. But I have no idea, if it compares to current x86 initialization or is more like in the old days. What tasks would there be, when – as you noted in your proposal – the development does not arrive in time or there are other problems? If I am not mistaken, you mentioned, you have some Intel GM45 Dell laptop with DDR2 memory. Could (start) implementing support for that be a backup task? Thanks, Paul > [1]: > https://docs.google.com/document/d/1Ex1rP7Y9kX4y5TQCx28uZyqx8iSgih_JyVGnM3fltL8/edit?usp=sharing
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