> I didn’t see that the D_LCK bit was set anywhere so does that mean I can potentially let SeaBIOS install an SMI handler?
Isn't it that D_LCK belongs to the following PCIe root hub configuration space register: 0:0.0 0x9c (32bit)? Where the following is the lowest byte structure: bit 7 -> Reserved bit 6 -> D_OPEN bit 5 -> D_CLS bit 4 -> D_LCK bit 3 -> Enable [bits (0..2) are reserved (0s)] When I do the following on my HSW i5-4300: setpci -s 0:0.0 0x9c.l => 0xFFFFFFFF ??? Any explanation? York? Thank you, Zoran On Fri, Sep 23, 2016 at 1:27 AM, Watzlavick, Robert L < [email protected]> wrote: > I want to experiment with an SMI handler on the Camelback Mountain CRB > (Xeon D-1500) but it appears that the fsp_broadwell_de changes removed SMM > support. I’m browsing the coreboot-4.4 release. Was there a reason it was > removed? It shows up in the soc/intel/Broadwell area so I suppose I could > port over the original code. I didn’t see that the D_LCK bit was set > anywhere so does that mean I can potentially let SeaBIOS install an SMI > handler? Or is it set in the FSP? I also noticed the mainline has some > new code under coreboot/src/soc/intel/sch but I’m not sure which processors > that is for. > > > > Thanks, > > -Bob > > -- > coreboot mailing list: [email protected] > https://www.coreboot.org/mailman/listinfo/coreboot >
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