On 10/10/2016 21:59, Rudolf Marek wrote: > Hi Andriy, > >> An example: >> $ ioapic_wr 3 0xff00000000000300 > > I tried with minicom and IRQ 4, and I can confirm that NMI is delivered only > when using the redirection entry above. The one 0x0000000000000400 does > nothing > in my case. I tested on AMD Hudson chipset,
It would be interesting to test 0x00...300 and 0xff...400 just for completeness. > I had to add #include <stdint.h> to > have the proper type defines under Linux. I'll also add this one just in case. > The NMI arrived to all CPUs, Linux said: > > Oct 10 20:51:08 ruik kernel: [ 891.596625] Uhhuh. NMI received for unknown > reason 31 on CPU 2. > Oct 10 20:51:08 ruik kernel: [ 891.596631] Uhhuh. NMI received for unknown > reason 31 on CPU 1. > Oct 10 20:51:08 ruik kernel: [ 891.596633] Uhhuh. NMI received for unknown > reason 31 on CPU 0. > Oct 10 20:51:08 ruik kernel: [ 891.596636] Uhhuh. NMI received for unknown > reason 31 on CPU 3. > Oct 10 20:51:08 ruik kernel: [ 891.596638] Do you have a strange power saving > mode enabled? > Oct 10 20:51:08 ruik kernel: [ 891.596639] Do you have a strange power saving > mode enabled? > Oct 10 20:51:08 ruik kernel: [ 891.596644] Do you have a strange power saving > mode enabled? > Oct 10 20:51:08 ruik kernel: [ 891.596646] Dazed and confused, but trying to > continue > Oct 10 20:51:08 ruik kernel: [ 891.596648] Dazed and confused, but trying to > continue > Oct 10 20:51:08 ruik kernel: [ 891.596652] Dazed and confused, but trying to > continue > Oct 10 20:51:08 ruik kernel: [ 891.596666] Do you have a strange power saving > mode enabled? > Oct 10 20:51:08 ruik kernel: [ 891.596670] Dazed and confused, but trying to > continue > > I can try to contact Mr. AMD ask them to at least publish new errata versions. That would be great. I am really curious about the official clarification on the issue. Maybe there is a configuration bit that they forgot to set or something like that. I found a really old document about AMD-8131 chipset which seems like something that later morphed into the APIC component of the southbrdiges and in that document they discuss APIC -> HT mapping quite extensively. I wonder what went wrong later on. In this copy of the document it's on page 67 http://www.tautec-electronics.de/Datenblaetter/Schaltkreise/AMD8131.pdf -- Andriy Gapon -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
