Hi, make clean, did help....thanks
now in the next stage, I got this error : Include CPU microcode in CBFS > 1. Generate from tree (CPU_MICROCODE_CBFS_GENERATE) 2. Include external microcode header files (CPU_MICROCODE_CBFS_EXTERNAL_HEADER) 3. Do not include microcode updates (CPU_MICROCODE_CBFS_NONE) choice[1-3]: 1 Microcode binary path and filename (CPU_UCODE_BINARIES) [] * * Northbridge * * * Southbridge * * * Super I/O * * * Embedded Controllers * Vboot non-volatile storage in CMOS. (VBOOT_VBNV_CMOS) [N/y/?] n Vboot non-volatile storage in EC. (VBOOT_VBNV_EC) [N/y/?] n Verify firmware with vboot. (VBOOT) [N/y/?] (NEW) y * * Generic Drivers * AS3722 RTC support (DRIVERS_AS3722_RTC) [N/y] n Realtek 8168 reset (REALTEK_8168_RESET) [N/y/?] n Serial port on SuperIO (DRIVERS_UART_8250IO) [Y/n] y Oxford OXPCIe952 (DRIVERS_UART_OXPCIE) [N/y/?] n UART's PCI bus, device, function address (UART_PCI_ADDR) [0x0] 0x0 USB 2.0 EHCI debug dongle support (USBDEBUG) [N/y/?] (NEW) y Enable early (pre-RAM) usbdebug (USBDEBUG_IN_ROMSTAGE) [Y/n/?] (NEW) y Type of dongle > 1. Net20DC or compatible (USBDEBUG_DONGLE_STD) (NEW) 2. BeagleBone (USBDEBUG_DONGLE_BEAGLEBONE) (NEW) 3. BeagleBone Black (USBDEBUG_DONGLE_BEAGLEBONE_BLACK) (NEW) 4. FTDI FT232H UART (USBDEBUG_DONGLE_FTDI_FT232H) (NEW) choice[1-4]: 1 I2C TPM (I2C_TPM) [Y] (NEW) y I2C TPM Driver > 1. Generic I2C TPM Driver (I2C_TPM_GENERIC) (NEW) 2. CR50 I2C TPM Driver (I2C_TPM_CR50) (NEW) choice[1-2]: 1 I2C TPM chip bus (DRIVER_TPM_I2C_BUS) [0x9] (NEW) 1 I2C TPM chip address (DRIVER_TPM_I2C_ADDR) [0x2] (NEW) 0x2 IRQ or GPE to use for TPM interrupt (DRIVER_TPM_I2C_IRQ) [-1] (NEW) 18 Generate I2C TPM ACPI device (DRIVER_I2C_TPM_ACPI) [N/y] n Support Intel PCI-e WiFi adapters (DRIVERS_INTEL_WIFI) [Y/n/?] y PS/2 keyboard init (DRIVERS_PS2_KEYBOARD) [N/y/?] n Silicon Image SIL3114 (DRIVERS_SIL_3114) [N/y/?] n TI TPS65913 support (DRIVERS_TI_TPS65913) [N/y] n TI TPS65913 RTC support (DRIVERS_TI_TPS65913_RTC) [N/y] n * * Console * Squelch AP CPUs from early console. (SQUELCH_EARLY_SMP) [Y/n/?] y Serial port console output (CONSOLE_SERIAL) [Y/n/?] y * * I/O mapped, 8250-compatible * Index for UART port to use for console (UART_FOR_CONSOLE) [0] 0 * * Serial port base address = 0x3f8 * Baud rate 1. 921600 (CONSOLE_SERIAL_921600) 2. 460800 (CONSOLE_SERIAL_460800) 3. 230400 (CONSOLE_SERIAL_230400) > 4. 115200 (CONSOLE_SERIAL_115200) 5. 57600 (CONSOLE_SERIAL_57600) 6. 38400 (CONSOLE_SERIAL_38400) 7. 19200 (CONSOLE_SERIAL_19200) 8. 9600 (CONSOLE_SERIAL_9600) choice[1-8]: 4 spkmodem (console on speaker) console output (SPKMODEM) [N/y/?] n USB dongle console output (CONSOLE_USB) [N/y/?] (NEW) y Use onboard VGA as primary video device (ONBOARD_VGA_IS_PRIMARY) [N/y/?] n Network console over NE2000 compatible Ethernet adapter (CONSOLE_NE2K) [N/y/?] n Send console output to a CBMEM buffer (CONSOLE_CBMEM) [Y/n/?] y Room allocated for console output in CBMEM (CONSOLE_CBMEM_BUFFER_SIZE) [0x20000] 0x20000 Default console log level > 1. 8: SPEW (DEFAULT_CONSOLE_LOGLEVEL_8) 2. 7: DEBUG (DEFAULT_CONSOLE_LOGLEVEL_7) 3. 6: INFO (DEFAULT_CONSOLE_LOGLEVEL_6) 4. 5: NOTICE (DEFAULT_CONSOLE_LOGLEVEL_5) 5. 4: WARNING (DEFAULT_CONSOLE_LOGLEVEL_4) 6. 3: ERR (DEFAULT_CONSOLE_LOGLEVEL_3) 7. 2: CRIT (DEFAULT_CONSOLE_LOGLEVEL_2) 8. 1: ALERT (DEFAULT_CONSOLE_LOGLEVEL_1) 9. 0: EMERG (DEFAULT_CONSOLE_LOGLEVEL_0) choice[1-9]: 1 Don't show any POST codes (NO_POST) [N/y] n Store post codes in CMOS for debugging (CMOS_POST) [N/y/?] n Show POST codes on the debug console (CONSOLE_POST) [N/y/?] n Send POST codes to an external device (POST_DEVICE) [Y/n] y Device to send POST codes to > 1. None (POST_DEVICE_NONE) 2. LPC (POST_DEVICE_LPC) 3. PCI/PCIe (POST_DEVICE_PCI_PCIE) choice[1-3]: 1 Send POST codes to an IO port (POST_IO) [Y/n/?] y IO port for POST codes (POST_IO_PORT) [0x80] 0x80 * * Debugging * GDB debugging support (GDB_STUB) [Y/n/?] y Wait for a GDB connection (GDB_WAIT) [N/y/?] n Halt when hitting a BUG() or assertion error (FATAL_ASSERTS) [N/y/?] n Output verbose CBFS debug messages (DEBUG_CBFS) [Y/n/?] y Output verbose RAM init debug messages (DEBUG_RAM_SETUP) [N/y/?] n Check PIRQ table consistency (DEBUG_PIRQ) [Y/n/?] y Output verbose SMI debug messages (DEBUG_SMI) [N/y/?] (NEW) y Debug SMM relocation code (DEBUG_SMM_RELOCATION) [N/y/?] (NEW) y Output verbose malloc debug messages (DEBUG_MALLOC) [Y/n/?] y Output verbose ACPI debug messages (DEBUG_ACPI) [Y/n/?] y Output verbose TPM debug messages (DEBUG_TPM) [N/y/?] (NEW) y Output verbose USB 2.0 EHCI debug dongle messages (DEBUG_USBDEBUG) [N/y/?] (NEW) y Trace function calls (TRACE) [Y/n/?] y Debug boot state machine (DEBUG_BOOT_STATE) [Y/n/?] y * * Restart config... * * * Chipset * * * SoC * * * CPU * Include CPU microcode in CBFS > 1. Generate from tree (CPU_MICROCODE_CBFS_GENERATE) 2. Include external microcode header files (CPU_MICROCODE_CBFS_EXTERNAL_HEADER) 3. Do not include microcode updates (CPU_MICROCODE_CBFS_NONE) choice[1-3]: 1 Microcode binary path and filename (CPU_UCODE_BINARIES) [] * * Northbridge * * * Southbridge * * * Super I/O * * * Embedded Controllers * Vboot non-volatile storage in CMOS. (VBOOT_VBNV_CMOS) [N/y/?] n Vboot non-volatile storage in EC. (VBOOT_VBNV_EC) [N/y/?] n Vboot starts verifying in bootblock (VBOOT_STARTS_IN_BOOTBLOCK) [N/y/?] (NEW) y Mock secdata for firmware verification (VBOOT_MOCK_SECDATA) [N/y/?] (NEW) y Disable dev mode on recovery requests (VBOOT_DISABLE_DEV_ON_RECOVERY) [N/y/?] (NEW) y Vboot verification is built into a separate stage (SEPARATE_VERSTAGE) [N/y] (NEW) y The separate verification stage returns to its caller (RETURN_FROM_VERSTAGE) [N/y/?] (NEW) y The chipset provides the main() entry point for verstage (CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL) [N/y/?] (NEW) y Vboot's work buffer is dynamically allocated. (VBOOT_DYNAMIC_WORK_BUFFER) [N/y/?] (NEW) y Video option ROM matters (= can skip display init) (VBOOT_OPROM_MATTERS) [N/y/?] (NEW) y Verify firmware with vboot. (VBOOT) [Y/n/?] y # # configuration written to /home/bianchi/coreboot/.config # HOSTCC util/sconfig/lex.yy.o HOSTCC util/sconfig/sconfig.tab.o HOSTCC util/sconfig/main.o HOSTCC util/sconfig/sconfig (link) SCONFIG mainboard/intel/i946gz/devicetree.cb HOSTCC nvramtool/cli/nvramtool.o HOSTCC nvramtool/cli/opts.o HOSTCC nvramtool/cmos_lowlevel.o HOSTCC nvramtool/cmos_ops.o HOSTCC nvramtool/common.o HOSTCC nvramtool/compute_ip_checksum.o HOSTCC nvramtool/hexdump.o HOSTCC nvramtool/input_file.o HOSTCC nvramtool/layout.o HOSTCC nvramtool/accessors/layout-common.o HOSTCC nvramtool/accessors/layout-text.o HOSTCC nvramtool/accessors/layout-bin.o HOSTCC nvramtool/lbtable.o HOSTCC nvramtool/reg_expr.o HOSTCC nvramtool/cbfs.o HOSTCC nvramtool/accessors/cmos-mem.o HOSTCC nvramtool/nvramtool (link) OPTION option_table.h CC bootblock/mainboard/intel/i946gz/static.o CC bootblock/arch/x86/boot.o GEN generated/bootblock.ld CP bootblock/arch/x86/bootblock.ld HOSTCC util/romcc/romcc (this may take a while) ROMCC generated/bootblock.inc CC bootblock/arch/x86/bootblock_romcc.o CC bootblock/arch/x86/cpu_common.o GEN build.h CC bootblock/arch/x86/id.o CC bootblock/arch/x86/memcpy.o CC bootblock/arch/x86/memset.o CC bootblock/arch/x86/mmap_boot.o CC bootblock/arch/x86/walkcbfs.o CC bootblock/commonlib/cbfs.o CC bootblock/commonlib/lz4_wrapper.o CC bootblock/commonlib/mem_pool.o CC bootblock/commonlib/region.o CC bootblock/console/die.o CC bootblock/console/post.o CC bootblock/cpu/x86/lapic/boot_cpu.o CC bootblock/cpu/x86/mtrr/earlymtrr.o CC bootblock/device/device_simple.o CC bootblock/device/i2c.o CC bootblock/drivers/uart/uart8250io.o CC bootblock/drivers/uart/util.o CC bootblock/lib/boot_device.o CC bootblock/lib/bootmode.o HOSTCC cbfstool/fmaptool.o HOSTCC cbfstool/cbfs_sections.o HOSTCC cbfstool/fmap_from_fmd.o HOSTCC cbfstool/fmd.o HOSTCC cbfstool/fmd_parser.o HOSTCC cbfstool/fmd_scanner.o HOSTCC cbfstool/fmap.o HOSTCC cbfstool/kv_pair.o HOSTCC cbfstool/valstr.o HOSTCC cbfstool/fmaptool (link) FMAP build/util/cbfstool/fmaptool -h build/fmap_config.h build/fmap.fmd build/fmap.fmap SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header) The sections containing CBFSes are: COREBOOT CC bootblock/lib/cbfs.o CC bootblock/lib/cbmem_console.o CC bootblock/lib/delay.o CC bootblock/lib/fmap.o CC bootblock/lib/gcc.o CC bootblock/lib/halt.o CC bootblock/lib/hexdump.o CC bootblock/lib/libgcc.o CC bootblock/lib/memchr.o CC bootblock/lib/memcmp.o CC bootblock/lib/prog_loaders.o CC bootblock/lib/prog_ops.o CC bootblock/lib/version.o CC bootblock/vboot/bootmode.o LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.bin CC romstage/mainboard/intel/i946gz/static.o CC romstage/arch/x86/acpi_s3.o GEN generated/assembly.inc CC romstage/arch/x86/assembly_entry.o CC romstage/arch/x86/boot.o CC romstage/arch/x86/cbfs_and_run.o CC romstage/arch/x86/cbmem.o CC romstage/arch/x86/cpu_common.o CC romstage/arch/x86/memcpy.o CP romstage/arch/x86/memlayout.ld CC romstage/arch/x86/memmove.o CC romstage/arch/x86/memset.o CC romstage/arch/x86/mmap_boot.o CC romstage/arch/x86/postcar_loader.o CC romstage/commonlib/cbfs.o CC romstage/commonlib/lz4_wrapper.o CC romstage/commonlib/mem_pool.o CC romstage/commonlib/region.o CC romstage/console/console.o CC romstage/console/die.o CC romstage/console/init.o CC romstage/console/post.o CC romstage/console/printk.o CC romstage/console/vtxprintf.o CC romstage/cpu/intel/car/romstage.o CC romstage/cpu/intel/microcode/microcode.o CC romstage/cpu/x86/car.o CC romstage/cpu/x86/lapic/apic_timer.o CC romstage/cpu/x86/lapic/boot_cpu.o CC romstage/cpu/x86/mtrr/earlymtrr.o CC romstage/device/device_simple.o CC romstage/device/i2c.o CC romstage/device/pci_early.o CC romstage/drivers/pc80/rtc/mc146818rtc.o CC romstage/drivers/pc80/rtc/mc146818rtc_early.o CC romstage/drivers/uart/uart8250io.o CC romstage/drivers/uart/util.o CC romstage/lib/boot_device.o CC romstage/lib/bootmode.o CC romstage/lib/cbfs.o CC romstage/lib/cbmem_common.o CC romstage/lib/cbmem_console.o CC romstage/lib/compute_ip_checksum.o CC romstage/lib/delay.o CC romstage/lib/fmap.o CC romstage/lib/gcc.o CC romstage/lib/halt.o CC romstage/lib/hexdump.o CC romstage/lib/imd.o CC romstage/lib/imd_cbmem.o CC romstage/lib/libgcc.o CC romstage/lib/lzma.o CC romstage/lib/lzmadecode.o CC romstage/lib/memchr.o CC romstage/lib/memcmp.o CC romstage/lib/memrange.o CC romstage/lib/prog_loaders.o CC romstage/lib/prog_ops.o CP romstage/lib/program.ld CC romstage/lib/ramtest.o CC romstage/lib/romstage_stack.o CC romstage/lib/stack.o CC romstage/lib/version.o CC romstage/mainboard/intel/i946gz/romstage.o CC romstage/northbridge/intel/i945/debug.o CC romstage/northbridge/intel/i945/early_init.o CC romstage/northbridge/intel/i945/errata.o CC romstage/northbridge/intel/i945/ram_calc.o CC romstage/northbridge/intel/i945/raminit.o CC romstage/superio/ite/common/early_serial.o CC romstage/superio/ite/it8718f/early_serial.o CC romstage/vboot/bootmode.o LINK cbfs/fallback/romstage.debug /home/bianchi/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full build/romstage/console/console.o: In function `__usb_tx_byte': /home/bianchi/coreboot/src/include/console/usb.h:38: undefined reference to `usb_tx_byte' /home/bianchi/coreboot/src/include/console/usb.h:38: undefined reference to `usb_tx_byte' build/romstage/console/console.o: In function `__usb_tx_flush': /home/bianchi/coreboot/src/include/console/usb.h:39: undefined reference to `usb_tx_flush' src/arch/x86/Makefile.inc:264: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 bianchi@ubuntu:~/coreboot$ How can I fix that ? I can give you the complete code on i946gz if you want to reproduce in your computer...I'm changing only romstage.c so far I attached with this email... Regards, Riko
/* * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> #include <string.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> #include <arch/acpi.h> #include <cbmem.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> //#include <superio/ite/lpc47m15x/lpc47m15x.h> //Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e //#include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> //Patch by bianchi 15 Oct 16 10:46AM //#include <southbridge/intel/i82801gx/early_lpc.c> //s#include <southbridge/intel/i82801gx/early_smbus.c> //#include <southbridge/intel/i82801gx/lpc.c> //Patch by bianchi 15 Oct 16 10:46AM //#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) //#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) //#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) void setup_ich7_gpios(void) { /* TODO: This is highly board specific and should be moved */ //printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ //outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ //outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ //outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ /* Output Control Registers */ //outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ /* Input Control Registers */ //outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ //outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ //outl(0x000000bf, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ //outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ /*updated from intel tool for i946GZ*/ /* TODO: This is highly board specific and should be moved */ printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ outl(0x1f3ff7c3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xe27effc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ /* Output Control Registers */ outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ /* Input Control Registers */ outl(0x00003900, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } static void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // Enable COM1 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); // Enable SuperIO Power Management Events pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); } static void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; /* Device 1d interrupt pin register */ RCBA32(0x310c) = 0x00214321; /* dev irq route register */ RCBA16(0x3140) = 0x0132; RCBA16(0x3142) = 0x0146; RCBA16(0x3144) = 0x0237; RCBA16(0x3146) = 0x3201; RCBA16(0x3148) = 0x0146; /* Enable IOAPIC */ RCBA8(0x31ff) = 0x03; /* Disable unused devices */ //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA; // RCBA32(0x3418) |= (1 << 0); // Required. // FIXME look me up! RCBA32(0x3418) = 0x003204e1; /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } static void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; // program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); RCBA32(0x0088) = 0x0011d000; RCBA16(0x01fc) = 0x060f; RCBA32(0x01f4) = 0x86000040; RCBA32(0x0214) = 0x10030549; RCBA32(0x0218) = 0x00020504; RCBA8(0x0220) = 0xc5; reg32 = RCBA32(0x3410); reg32 |= (1 << 6); RCBA32(0x3410) = reg32; reg32 = RCBA32(0x3430); reg32 &= ~(3 << 0); reg32 |= (1 << 0); RCBA32(0x3430) = reg32; RCBA32(0x3418) |= (1 << 0); RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; RCBA16(0x3e08) |= (1 << 7); RCBA16(0x3e48) |= (1 << 7); RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); // next step only on ich7m b0 and later: reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; if (bist == 0) enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ //lpc47m15x_enable_serial(PME_DEV, 0x680); //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ //enable_dev(SERIAL_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(GPIO_DEV); /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : boot_mode, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }
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