Everyone,
I got POST 0xFFFF then loop, and UART = 00
I have rewritten the ich7_enable_lpc function, and the complete
romstage.c attached, what do I miss here ? Does enable_lapic();
function depend to the board or it can run on 946 even it's written
for 945?
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// Enable COM1
//pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); //from
sudo lspci -xxx -s 0:1F.0
// Enable SuperIO Power Management Events
//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84,
0x003C0801);//from sudo lspci -xxx -s 0:1F.0, Idwer suggestion
}
bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
>> [sudo] password for bianchi:
>> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
>> Interface Bridge (rev 01)
>> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
>> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
>> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
>> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
>> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
>> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
>> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
>> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h>
//#include <superio/ite/lpc47m15x/lpc47m15x.h>
//Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e
//#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8718F_GPIO)
#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) //Patch on 28 October 2016
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
//#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
void setup_ich7_gpios(void)
{
/* TODO: This is highly board specific and should be moved */
//printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
//outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
//outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
//outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
/* Output Control Registers */
//outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */
//outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
//outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
//outl(0x000000bf, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
//outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
/*updated from intel tool for i946GZ*/
/* TODO: This is highly board specific and should be moved */
printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
outl(0x1f3ff7c3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xe27effc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
/* Output Control Registers */
outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */
outl(0x00003900, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
}
/*
static void setup_sio(void)
{*/
/* Set default GPIOs on superio */
/* ite_reg_write(GPIO_DEV, 0x25, 0x40);
ite_reg_write(GPIO_DEV, 0x26, 0x3f);
ite_reg_write(GPIO_DEV, 0x28, 0x41);
ite_reg_write(GPIO_DEV, 0x29, 0x88);
ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
ite_reg_write(GPIO_DEV, 0x62, 0x08);
ite_reg_write(GPIO_DEV, 0x72, 0x00);
ite_reg_write(GPIO_DEV, 0x73, 0x38);
ite_reg_write(GPIO_DEV, 0xb1, 0x01);
ite_reg_write(GPIO_DEV, 0xb8, 0x80);
ite_reg_write(GPIO_DEV, 0xbb, 0x40);
ite_reg_write(GPIO_DEV, 0xc0, 0x00);
ite_reg_write(GPIO_DEV, 0xc3, 0x00);
ite_reg_write(GPIO_DEV, 0xc8, 0x00);
ite_reg_write(GPIO_DEV, 0xcb, 0x00);
ite_reg_write(GPIO_DEV, 0xf6, 0x26);
ite_reg_write(GPIO_DEV, 0xfc, 0x4a);
*/
/*
ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
}
*/
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// Enable COM1
//pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); //from sudo lspci -xxx -s 0:1F.0
// Enable SuperIO Power Management Events
//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003C0801);//from sudo lspci -xxx -s 0:1F.0, Idwer suggestion
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
// FIXME look me up!
RCBA32(0x3418) = 0x003204e1;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
static void early_ich7_init(void)
{
uint8_t reg8;
uint32_t reg32;
// program secondary mlt XXX byte?
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
reg8 &= ~(1 << 2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
// usb transient disconnect
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
reg32 |= (1 << 29) | (1 << 17);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
RCBA32(0x01f4) = 0x86000040;
RCBA32(0x0214) = 0x10030549;
RCBA32(0x0218) = 0x00020504;
RCBA8(0x0220) = 0xc5;
reg32 = RCBA32(0x3410);
reg32 |= (1 << 6);
RCBA32(0x3410) = reg32;
reg32 = RCBA32(0x3430);
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
RCBA32(0x3418) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
RCBA16(0x3e48) |= (1 << 7);
RCBA32(0x3e0e) |= (1 << 7);
RCBA32(0x3e4e) |= (1 << 7);
// next step only on ich7m b0 and later:
reg32 = RCBA32(0x2034);
reg32 &= ~(0x0f << 16);
reg32 |= (5 << 16);
RCBA32(0x2034) = reg32;
}
void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
if (bist == 0)
enable_lapic();
ich7_enable_lpc();
post_code(0xD1);
/* Enable SuperIO PM */
//setup_sio();
//ite_conf_clkin();//needs a parameter, what is it ?
/*
04:24:31 AM) idwer: 24 or 48 MHz?
(04:25:18 AM) idwer: how do you find out? run superiotool when having booted with the vendor bios, and look at register CR23
*/
//ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
//post_code(pnp_read_config(dev, ITE_CONFIG_REG_CLOCKSEL)); //read value from IT8718F 0x23 register
//it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Disable SIO reboot */
//ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
ite_kill_watchdog(GPIO_DEV);
/* Set up the console */
console_init();
halt();
post_code(0xD2);
printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
post_code(0xD3);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
post_code(0xD4);
i945_early_initialization();
post_code(0xD5);
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}
--
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