Hi all, I am planning to do a cleanup of AMD Fam10-15 codebase, (i.e., not AGESA). I have currently completed a first attempt at removing most of the ".c" includes in romstage.
It currently builds on one board only, KFSN4-DRE, and only works on DDR2, (DDR3 is WIP). I would really appreciate someone to take a look at the headers and comment so I can get a picture of how strict coreboot would like to be in terms of the header layout. As in, I don't want to touch 24 boards until I have an idea of how it should be laid out. Obviously this is going to be a massive cleanup and will need testing on hardware, I was hoping to use REACTS as a first step once I get things working. Any suggestions welcome before I begin to address Kyosti's comments in a new push. Damien -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
