On Mon, Dec 12, 2016 at 2:58 PM, Trammell Hudson <[email protected]> wrote: > On Mon, Dec 12, 2016 at 01:14:58PM -0600, Aaron Durbin via coreboot wrote: >> Can you provide the isal -d dumps of before and after for your board? >> I think in one they'll be in SSDT and the other in DSDT. They should >> reside in /sys/firmware/acpi/tables/ that you can copy them and run >> them through iasl -d. > > Here's the diff:
What about the SSDT? With the patch I think the device is in the SSDT -- not DSDT. Thus you are showing DSDT contents which are the equivalent of this file: https://review.coreboot.org/#/c/17425/12/src/drivers/pc80/tpm/acpi/tpm.asl > > --- ./no-tpm/DSDT.dsl 2016-12-12 15:46:55.909063709 -0500 > +++ ./yes-tpm/DSDT.dsl 2016-12-12 15:56:26.308433858 -0500 > @@ -5,13 +5,13 @@ > * > * Disassembling to symbolic ASL+ operators > * > - * Disassembly of DSDT, Mon Dec 12 15:46:55 2016 > + * Disassembly of DSDT, Mon Dec 12 15:56:26 2016 > * > * Original Table Header: > * Signature "DSDT" > - * Length 0x000033DC (13276) > + * Length 0x00003627 (13863) > * Revision 0x02 > - * Checksum 0x58 > + * Checksum 0x26 > * OEM ID "COREv4" > * OEM Table ID "COREBOOT" > * OEM Revision 0x20110725 (537986853) > @@ -36,7 +36,7 @@ > > Scope (\) > { > - Name (NVSA, 0xBFEC8000) > + Name (NVSA, 0xBFECB000) > } > > If (Zero) > @@ -3961,6 +3961,205 @@ > > Scope (_SB.PCI0.LPCB) > { > + Device (TPM) > + { > + Name (_HID, EisaId ("PNP0C31")) // _HID: Hardware ID > + Name (_CID, EisaId ("PNP0C31")) // _CID: Compatible ID > + Name (_UID, One) // _UID: Unique ID > + OperationRegion (TREG, SystemMemory, 0xFED40000, 0x5000) > + Field (TREG, ByteAcc, NoLock, Preserve) > + { > + Offset (0x08), > + , 3, > + ITPL, 2, > + Offset (0x0C), > + IVEC, 4, > + Offset (0xF00), > + DVID, 32 > + } > + > + Method (_STA, 0, NotSerialized) // _STA: Status > + { > + If (((DVID > Zero) && (DVID < 0xFFFFFFFF))) > + { > + Return (0x0F) > + } > + Else > + { > + Return (Zero) > + } > + } > + > + Name (IBUF, ResourceTemplate () > + { > + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, > _Y02) > + { > + 0x00000000, > + } > + }) > + Name (RBUF, ResourceTemplate () > + { > + IO (Decode16, > + 0x002E, // Range Minimum > + 0x002E, // Range Maximum > + 0x01, // Alignment > + 0x02, // Length > + ) > + Memory32Fixed (ReadWrite, > + 0xFED40000, // Address Base > + 0x00005000, // Address Length > + ) > + }) > + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings > + { > + CreateField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._INT, 0x20, TVEC) > // _INT: Interrupts > + CreateBitField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._HE, TTYP) // > _HE_: High-Edge > + CreateBitField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._LL, TPOL) // > _LL_: Low Level > + CreateBitField (IBUF, \_SB.PCI0.LPCB.TPM._Y02._SHR, TSHR) > // _SHR: Sharable > + If (Zero) > + { > + TVEC = Zero > + TPOL = One > + TTYP = Zero > + TSHR = One > + Return (ConcatenateResTemplate (RBUF, IBUF)) > + } > + Else > + { > + If ((IVEC > Zero)) > + { > + TVEC = IVEC /* \_SB_.PCI0.LPCB.TPM_.IVEC */ > + If ((ITPL == Zero)) > + { > + TPOL = Zero > + TTYP = Zero > + TSHR = One > + } > + Else > + { > + If ((ITPL == One)) > + { > + TPOL = One > + TTYP = Zero > + TSHR = One > + } > + Else > + { > + If ((ITPL == 0x02)) > + { > + TPOL = Zero > + TTYP = One > + TSHR = Zero > + } > + Else > + { > + If ((ITPL == 0x03)) > + { > + TPOL = One > + TTYP = One > + TSHR = Zero > + } > + } > + } > + } > + > + Return (ConcatenateResTemplate (RBUF, IBUF)) > + } > + Else > + { > + Return (RBUF) /* \_SB_.PCI0.LPCB.TPM_.RBUF */ > + } > + } > + } > + > + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method > + { > + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") > /* Physical Presence Interface */)) > + { > + If ((Arg2 == Zero)) > + { > + Return (Buffer (0x02) > + { > + 0xFF, 0x01 > /* .. */ > + }) > + } > + > + If ((Arg2 == One)) > + { > + Return ("1.2") > + } > + > + If ((Arg2 == 0x02)) > + { > + Return (Zero) > + } > + > + If ((Arg2 == 0x03)) > + { > + Return (Package (0x02) > + { > + Zero, > + Zero > + }) > + } > + > + If ((Arg2 == 0x04)) > + { > + Return (0x02) > + } > + > + If ((Arg2 == 0x05)) > + { > + Return (Package (0x03) > + { > + Zero, > + Zero, > + Zero > + }) > + } > + > + If ((Arg2 == 0x06)) > + { > + Return (0x03) > + } > + > + If ((Arg2 == 0x07)) > + { > + Return (0x03) > + } > + > + If ((Arg2 == 0x08)) > + { > + Return (One) > + } > + > + Return (One) > + } > + > + If ((Arg0 == ToUUID > ("376054ed-cc13-4675-901c-4756d7f2d45d"))) > + { > + If ((Arg2 == Zero)) > + { > + Return (Buffer (One) > + { > + 0x03 > /* . */ > + }) > + } > + > + If ((Arg2 == One)) > + { > + Return (Zero) > + } > + > + Return (One) > + } > + > + Return (Buffer (One) > + { > + 0x00 /* . */ > + }) > + } > + } > } > > Name (_S0, Package (0x04) // _S0_: S0 System State > > -- > Trammell -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
