I have a problem with USB EHCI on board with Lynxpoint-LP southbridge. First of all system doesn't wakeup from USB devices from S3. EHCI controller is listed in "/proc/acpi/wakeup" as "enabled" and GPE number is seemed to be configured correctly to PME_B0, but it doesn't work.
More troubling issue that USB stops working after wakeup (for example from power button). In attempt to solve this issue I started to investigate how exactly EHCI works in S3 suspend/resume sequence. And I have some questions: 1) PCI_config: PWR_CNTL_STS register (54-55h) What power state should enter EHCI controller when system enters S3? D0 state or D3hot ? 2) MEM_BASE: USB2.0_CMD (20-23h) Is it correct, that system disables "Run/Stop (RS)" bit when system enters S3? 3) MEM_BASE: RMHPORTSTSN (F0h) Is it correct, that all ports became suspended when system enters S3? 4) Who is responsible to set "Run/Stop (RS)" and bring USB ports from suspended state? BIOS or OS? 5) Is there any board in coreboot that has USB EHCI working correctly with S3 suspend/resume? -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
