Hello! Thanks for an answer! Yes, it’s the same board. (Haswell ULT + Lynxpoint)
This is a custom board, so I don’t push it to coreboot repository, and therefore it is kinda hard for me to keep up to date with coreboot project. So I’ve fixed on some stable release and developed from there. Again, board is custom, so you’re right, there is no proprietary BIOS. There is definitely overlapping of some kind. I at least want to know the source of it. Is this problem caused by iPXE image or Coreboot/Seabios allocation? I'll try to port my coreboot changes to the newest release someday, but now it sounds like a shot in the dark. From: Zoran Stojsavljevic [mailto:[email protected]] Sent: Thursday, December 29, 2016 1:12 PM To: Аладышев Константин Cc: coreboot Subject: Re: [coreboot] iPXE on multiple chips with the same PCI ID Hello Konstantin, Seems that your board plays kind of fiber based GIGa router with several (max. 10) optical i/f attached. Insinuates the same board from the previous email. Correct? Here is what CPU is used: https://ark.intel.com/products/75114/Intel-Core-i7-4650U-Processor-4M-Cache-up-to-3_30-GHz (CPUID - 0x40651). Glanced via attached log. Yup, there are all visible, and in early stage there are some resource allocations for all three I350 devices/PCIe buses, seems that these resources overlap per device (in early stages). Could not say with 100% certainty. Lot of kludges, assumptions... But let us take the different route, for now (to save the time). Questions to you: [1] Why you are using very old Coreboot build 4.0 (coreboot-4.0-8341-g5e6dd5f-dirty Thu Mar 19 10:15:27 UTC 2015)??? [2] Did you ever use BIOS for this router? How does BIOS behave in the term of PXE booting? I start doubting that customized/tailored BIOS ever existed for this proprietary HSW built board!? TO DO: [1] To rebuild Coreboot with the latest and greatest Coreboot 4.5, and repeat the tests again? Please, let us know! :-) Zoran On Wed, Dec 28, 2016 at 3:17 PM, Аладышев Константин <[email protected]> wrote: I have a board with multiple external PCIe Ethernet I350 chips. In my lspci I have: 03.00.0 (4-port I350) 03.00.1 03.00.2 03.00.3 04.00.0 (4-port I350) 04.00.1 04.00.2 04.00.3 05.00.0 (2-port I350) 05.00.1 I builtin iPXE image to coreboot and I have all of these devices in Seabios bootmenu. But the problem is that I can only boot from ports of the first appeared chip. In the example above it will be 03.00.x boot devices. If I’ll physically unplug 03.00.x chip, I’ll be able to boot from 04.00.x boot devices. And if I’ll unplug 03.00.x and 04.00.x chip, I’ll be able to boot from 05.00.x boot devices. Does someone had the same problem and how to solve it? Coreboot+SeaBIOS log is in attachment (it has some additional printk’s) -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
