Hello everyone, Thanks to some help on IRC the culprit causing the "pci" errors was found. Disabling the hardware monitoring part of the Super I/O causes the error to disappear.
Current state is that linux boots with "acpi=off" in the cmdline. With ACPI the system crashes. A bootlog of linux booting using coreboot on the X9SPU-F with ACPI enabled, showing the crash, can be found here: https://gist.github.com/rnplus/99866582dd692557ecccd11a3920edcd Now that things (sort of) work (linux can boot using acpi=off and the graphics card works using an extracted vgabios) I would like to learn how to solve the remaining issues. The first issue is the hardware monitoring: why does coreboot crash and what changes to the devicetree should I make to get the hardware monitoring to function? The second issue is that Coreboot always tries to enable the IGD (Intel graphics), even when using a CPU without IGD (Xeon) and without the Intel VGABIOS. This results in a crash obviously. To disable the IGD I put a "return 0;" at the start of the "init_igd_opregion" function in "src/northbridge/intel/sandybridge/acpi.c". Is this the only way to disable IGD or could there be a better place to stop the IGD code from being run? I think a kconfig parameter like "DISABLE_IGD" could be a solution, but how are things like this normally solved? Also: when there is no VBIOS then maybe the IGD should not be initialized as well. I suggest doing something with the return value of "init_opregion_vbt(opregion)", stopping the IGD init when loading the VBIOS has failed. I suspect the ACPI issues also have to do with the IGD. Could someone confirm this? So the actual question is: What would be the best way to disable all IGD related code when using a board that will never make use of the IGD? (The Supermicro X9SPU-F board has a separate PCIe graphics chip [WPCM450] which is used for video output) More information can be found here: https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f The board code can be found here: https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f/tree/master/c oreboot/src/mainboard/supermicro/x9spu-f Thank you all for your help! Greetings, Renze Nicolai On zo, 2017-01-15 at 15:28 +0100, Renze Nicolai wrote: > Hello everyone, > > A small update: The serial port (finally) works! (apparently a > kconfig > entry was needed for the superio code to actually enable the serial > port when it is enabled in code) > > However the actual problem still remains: > The bootlog reports that something is wrong with the PCI(e) resources > and when the pci resources are being enabled the boot stops. > > Bootlog can be found here: > https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f/blob/master > /i > nfo/bootlog > > The board code as it is now can be found here: > https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f/tree/master > /c > oreboot-x9spu-f/src/mainboard/supermicro/x9spu-f > > What controls the pci resources? And where could the problem be? > > Also I don't understand where the "subsystemid" values in the device > tree come from and what they are used for. If someone could explain > that to me it would help as well. > > Greetings, > Renze Nicolai > > > > On Sat, 2017-01-14 at 21:31 +0100, Renze Nicolai wrote: > > Hello everyone, > > > > I am trying to port coreboot to the Supermicro X9SPU-F mainboard, > > starting with the code for the ga-b75m-d3v mainboard (which is also > > based on the Intel C216 chipset). > > > > I've put the code here: > > https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f/tree/mast > > er > > /c > > oreboot-x9spu-f/src/mainboard/supermicro/x9spu-f > > > > And I've put all the information that might be needed here: > > https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f/tree/mast > > er > > /i > > nfo > > > > Including a bootlog extracted using the PC speaker: > > https://github.com/rnplus/coreboot-dev-supermicro-x9spu-f/blob/mast > > er > > /i > > nfo/bootlog > > > > I did not get the serial ports to work yet. The mainboard has both > > a > > WPCM450 and a NCT6776F superio chip. I think the serial port on the > > back of the machine is connected to the NCT6776F chip, which is > > driven > > by the WPCM450. > > > > If anyone knows what I did wrong with the superio chips please do > > tell > > me! > > > > But the main problem is with the PCI express config: The board > > stops > > booting when it tries to enable the resources for PCI 00:1c.6 > > > > Earlier in the bootlog this message appears: > > > > ---- > > > > Setting resources... > > DOMAIN: 0000 io: base:65 size:203a align:12 gran:0 limit:2f7 > > !! Resource didn't fit !! > > aligned base 1000 size 1000 limit 2f7 > > 1fff needs to be <= 2f7 (limit) > > PCI: 00:1c.6 1c * [0x0 - 0xfff] io > > PCI: 00:1c.6 1c * [0x0 - 0xfff] io > > !! Resource didn't fit !! > > aligned base 1000 size 1000 limit 2f7 > > 1fff needs to be <= 2f7 (limit) > > PCI: 00:1c.7 1c * [0x1000 - 0x1fff] io > > ... > > !! Resource didn't fit !! > > aligned base 1000 size 20 limit 2f7 > > 101f needs to be <= 2f7 (limit) > > PCI: 05:00.0 18 * [0x0 - 0x1f] io > > > > ---- > > > > Where could these errors be coming from and how can I solve them? > > Did I make some kind of mistake in the devicetree.cb? > > > > Also: where do the values used in the "subsystemid" lines in the > > devicetree come from? > > > > > > Thank you! > > > > Greetings, > > Renze Nicolai > > > > -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
