Dear Coreboot Community, I am trying to understand the execution of coreboot’s ROM stage on my ASUS F2A85-M motherboard and was hoping to get your advice and guidance.
I have an ASUS F2A85-M motherboard with an AMD A6-5400K processor, and a single Kingston KVR1333D3N9/2G DDR3 DIMM memory in DIMM_A2. I followed the Lesson 1 guide for building coreboot (built with the coreinfo payload) and flashed the resulting image to the appropriate BIOS chip for the F2A85-M motherboard. Because my processor was not supported I needed to add the appropriate CPU device ID in src/cpu/amd/agesa/family15tn/model_15_init.c and switch the == to != on line 255 of src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c (I saw this hack in a previous exchange<https://www.coreboot.org/pipermail/coreboot/2014-February/077383.html>). The resulting defconfig of the build looks like this: CONFIG_VENDOR_ASUS=y CONFIG_BOARD_ASUS_F2A85_M=y CONFIG_CONSOLE_POST=y CONFIG_PAYLOAD_ELF=y CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf” I also have a serial port adapter (to USB) so that I can see the output of the coreboot process. Using this setup I am able to start up the machine with coreboot and get to the coreinfo screen (which I can then interact with). I am confused, however, by the output I am seeing from the boot process (attached). Specifically, it appears that the AmdInitReset procedure never exits, as shown below. coreboot-4.5-1349-g41dded3-dirty Mon Mar 20 03:04:09 UTC 2017 romstage starting... POST: 0x34 BSP Family_Model: 00610f21 cpu_init_detectedx = 00000000 POST: 0x37 AmdInitReset: Start *** !!AGESA cb_AgesaV0.0.0.1 *** FCH Reset Data Block Allocation: [0x0], Ptr = 0x004001e0 Fch OEM config in INIT RESET Done PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 subsystem <- 1022/1410 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0003 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0003 … Then, procedures like AmdInitPost are never called.. How then is the memory controller and DRAM being initialized and configured? I thought this was being done by AmdInitPost but it appears it is never running this code. I am especially confused as to how coreinfo can function (and read DRAM contents) without the memory controller and DRAM being configured first.. Based on the few examples<http://pastebin.com/2Lbew82b> of outputs for F2A85-M I can find online, this output seems to be an anomaly and I’d like to understand what may be causing AmdInitReset to not end properly and the processor to never enter cache-as-ram mode in the romstage. For reference, the last commit of my coreboot source is this<https://github.com/coreboot/coreboot/commit/41dded3548327d2cb6bd8845e78b94e51207f8f6> (which seems to be up-to-date at present). Thank you for any guidance you can provide on this issue; it is much appreciated! Best, Berj
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