On Fri, 30 Jun 2017 04:25:06 +0000
ron minnich <rminn...@gmail.com> wrote:

> there's something I am certain I don't understand about SMM on intel
> chipsets.
> 
> The question is pretty simple. Consider a system with a recent intel
> chipset and flash. Is there some special secret sauce that disables
> writing to flash unless in SMM and if so, what is it?

There is also a talk explaining it (without SMM_BWP).

https://media.ccc.de/v/31c3_-_6129_-_en_-_saal_2_-_201412282030_-_attacks_on_uefi_security_inspired_by_darth_venamis_s_misery_and_speed_racer_-_rafal_wojtczuk_-_corey_kallenberg

Attachment: pgphuIb2yHbvn.pgp
Description: OpenPGP digital signature

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Reply via email to