Thx - so, if I understand correctly you mean that I can handle the to chips separately? Which means: - first step: read the 8MB chip, apply me_cleaner, unlock it and write it back - second step: build coreboot (optionally with video bios extracted from original bios) and flash it to the 4MB chip If this is true, it would mean that I could now flash back just the 8MB of the stock firmware (applying me_cleaner and unlocking it before flashing) and it should work fine with the upper 4MB (that contain coreboot). I haven't tried that but I'm a little bit sceptical that it will work... Just in order to be clear about what I did (and what worked perfectly on the another Thinkpad x230 to which I installed the same coreboot/seabios/me_cleaner-configuration): - I extracted both 8MB + 4MB stock firmware and concatenated them to one 12MB image - I applied me_cleaner, unlocked it, extracted gbe.bin, me.bin, descriptor.bin and vbios.bin - I built a 12MB coreboot-image adding those binary blobs - I separated the image into lower 8MB and upper 4MB and flashed them back separately. As I've said it worked perfectly for the other x230 I have and I don't understand what's different with this one.
Am Tue, 04 Jul 2017 14:05:07 +0200 schrieb Martin Kepplinger <[email protected]>: > Am 03.07.2017 17:23 schrieb Marcel Maci: > > Hi, I've flashed coreboot with seaBIOS and me_cleaner to my Thinkpad > > x230 and everything works fine except the network. Neither wifi nor > > ethernet works. Could this be a problem with the gbe.bin I've used > > (I extracted it with ifdtool -x from the factory bios and the first > > time I did this on another Thinkpad x230 it worked perfectly)? > > You don't need to extract gbe.bin, descriptor.bin or me.bin for the > X230. I > planned to update the wiki a little because I also found it to be not > clear > enough: > > So you are talking about external SPI flashing. There are 2 flash > chips and > the gbe part is in the "second", 8MB one, together with the me and > descriptor > parts. You really "need" to access this chip only once. What you want > to do is > read it (obviously), run me_cleaner on it (you can use the whole > image. me_cleaner > will recognise it and write a new one for you), and run ifdtool -u on > it in order > to unlock internal writing from now on. That's it, so write that > back. Until > me_cleaner or the libreboot people find a way to *really* remove the > ME, I guess you don't have to touch that 8MB chip anymore. > > For the bios (coreboot with payload), you only need to access the > "first", 4MB > chip, and you don't need any extracted binary blob when building > coreboot for > this; they're part of the other one. (except for the video BIOS, if > you want to). > When flashing (writing) *externally*, of course you have to cut out > the 4MB > from the 12MB that the coreboot build creates for you, like seen in > the wiki. > > When flashing *internally*, you can use the 12MB image as is, and use > flashrom's > --layout feature, again using only the 4MB for flashing coreboot, > leaving all > the rest untouched. So again, you don't need any extracted binary > when building > coreboot. > > hope that helps. Although I use an Atheros wifi chip on PCIe, it > works just fine. > > martin > -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
