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On 09/17/2017 03:08 AM, Martin Roth wrote: Hi Martin, > Hi Tirumalesh, The patch for the main code is here: > https://review.coreboot.org/#/c/20861/ SOC code: > https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/denve rton_ns > > The only board that uses it right now is the CRB: > https://review.coreboot.org/#/c/20862/ Mainboard code: > https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/intel /harcuvar I > can't see any information about FSP. Is there FSP binary used for this platform ? Both with Tirumalesh we asked Intel, but they point to documentation that I have no access to. I would at least want to know what are the plans with Denverton support. Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlnAIb8ACgkQsu5x6Weq nkx99g//TnSQ0UQsmHBm7ydyHfW1mEyjbdTPe1v/9mcQWyR2G8n3+WWd+KB/3bFX ZwlTX/UpKmom3WJweKfjT5mDd+1BM/6fqNrGPTxfqm2mYK90o7kxqBLE5HzD0v1u Fa6ps+sEzU3RolZEbs6kVpPfz6e6IXM1lqBbfeDIXB92Jm3B9YUA4/NMHwrKYNjG VvfttR9R0wjrtCbni7qSV5GbzYAlkawuklEnmzxAn/N8QWRW6ndrrDXDBUuLPBAA RN3jG326WUQ50IFig1+1L9pw/a6edfhUh//+REeTrf8Ko+MZ5Pji2AWD9HScjLzW c493B0ccZm3B8o7b7lykaSHNiPdmrqsI7UfxsjeOzqVl57oNBsdj9LtLANwpdypI 88D/1/0+6X1BGqneIdfcul6Xwt7dSJ4JojEa03UFVT59lQMYqWE7Mt+v58SN+i5B zz6ORsXftmVAi48wnjPvteRo01K2mdi7OK/g+Gu4oQu5S9VTQJok5qf++Un8o9Ry 7T08Qecd/samnKfarfgK1MBM0ysASgmB7EDwpd3k/hWubpkFnVEtXpU8zSuZZzdE N8o8SwnqGUUhleyrcGRWNE1LdQ0KVR+OCOhVaFpncD91i2EJWfTQo978TEqfQGDG HwmeKl0OahjddHOXViUFgfb5MDPa2q7xPMRBWeLOqcvqI56Tc08= =O2U9 -----END PGP SIGNATURE----- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot