Hi Matt, Jay,
On 04.11.2017 03:25, Matt DeVillier wrote:
Hi Jay,
the SKL/KBL FSP blob published on Github is compatible with the headers
currently in coreboot, with the exception of the MEMORY_INFO_DATA_HOB - as
is, coreboot will not be able to parse the HOB and populate the SMBIOS
tables (minor adjustment needed, see: https://pastebin.com/Um9m7X43), but
otherwise it should boot and run without issue (at least it does on the
handful of SKL devices I've used it with, using both DDR3 and DDR4). The
FSP signatures absolutely should match, so I'm not sure why you're seeing
otherwise
I'm not sure what versions you are comparing, I see many more diffe-
rences between Kabylake FSP from github (54b6a31) and upstream sky-
kabylake in coreboot (b2b2015, see attachment). Also in UPD values
(SpiFlashCfgLockDown and ThreeStrikeCounterDisable were added to FSPS
UPD, the former is used in coreboot).
Do I miss something? Is there another more recent published binary?
Nico
-Matt
On Fri, Nov 3, 2017 at 7:26 PM, Jay Talbott <[email protected]
wrote:
I’m trying to get coreboot up and running on an Intel RVP15 CRB, which is
the same as the RVP7 except that the RVP15 has DDR4 memory instead of DDR3.
There is a mainboard solution for the RVP7 in coreboot. However, the
current KabyLake FSP published on GitHub doesn’t seem like it’s the right
FSP for the SkyLake-U/KabyLake-U. If nothing else, there’s a problem with
that FSP such that the signature in the FSP-M UPD header does not match the
signature in the corresponding header files, so when the FSP 2.0 driver in
coreboot goes to check that they are a match, execution dies right there.
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die("Invalid FSPM signature!\n");
(coreboot/src/drivers/intel/fsp2_0/memory_init.c, in function
do_fsp_memory_init)
I don’t want to bypass that check in the code in case the FSP posted to
GitHub isn’t the right FSP for this particular SoC…
Obviously, somebody at Intel has the right FSP that works for these boards
in order to validate that the coreboot implementation worked prior to
upstreaming it to the repo. I’m just not sure how to get the right one so
that I can get this booting.
Furthermore, I have yet to get the serial console working on the DB-9
serial port. I have the jumpers on the board configured to connect it to
UART #2, and configured in coreboot accordingly, but I get nothing for
console output.
Any help would be most appreciated!
Thanks,
- Jay
diff --git a/KabylakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h
b/KabylakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h
index 94ca784..c8cdc5f 100644
--- a/KabylakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h
+++ b/KabylakeFspBinPkg/Include/ConfigBlock/CpuConfigFspData.h
@@ -1,15 +1,22 @@
/** @file
FSP CPU Data Config Block.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available
under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@copyright
+ Copyright (c) 2016 Intel Corporation. All rights reserved
+ This software and associated documentation (if any) is furnished
+ under a license and may only be used or copied in accordance
+ with the terms of the license. Except as permitted by the
+ license, no part of this software or documentation may be
+ reproduced, stored in a retrieval system, or transmitted in any
+ form or by any means without the express written consent of
+ Intel Corporation.
+ This file contains an 'Intel Peripheral Driver' and is uniquely
+ identified as "Intel Reference Module" and is licensed for Intel
+ CPUs and chipsets under the terms of your license agreement with
+ Intel or your vendor. This file may be modified by the user, subject
+ to additional terms of the license agreement.
+@par Specification Reference:
**/
#ifndef _CPU_CONFIG_FSP_DATA_H_
#define _CPU_CONFIG_FSP_DATA_H_
@@ -56,10 +63,9 @@ typedef union {
UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon
Initialization will skip MP Initialization (including BSP) if enabled. For
non-FSP, this should always be 0.
UINT32 RsvdBits : 15; ///< Reserved for future
use
UINT32 Reserved;
- } Bits;
- UINT32 Uint32[2];
- } CPU_CONFIG_FSP_DATA;
-
+ } Bits;
+ UINT32 Uint32[2];
+} CPU_CONFIG_FSP_DATA;
#pragma pack (pop)
#endif // _CPU_CONFIG_FSP_DATA_H_
diff --git a/KabylakeFspBinPkg/Include/FspmUpd.h
b/KabylakeFspBinPkg/Include/FspmUpd.h
index 4bbc1aa..f3aa4c8 100644
--- a/KabylakeFspBinPkg/Include/FspmUpd.h
+++ b/KabylakeFspBinPkg/Include/FspmUpd.h
@@ -844,7 +844,7 @@ typedef struct {
/** Offset 0x02E3 - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is
always
- lower than the core ratio.<b>0: Disable</b>; 1: Enable.
+ lower than the core ratio. 0: Disable; <b>1: Enable.</b>
$EN_DIS
**/
UINT8 RingDownBin;
diff --git a/KabylakeFspBinPkg/Include/FspsUpd.h
b/KabylakeFspBinPkg/Include/FspsUpd.h
index e91bc79..f4f4bad 100644
--- a/KabylakeFspBinPkg/Include/FspsUpd.h
+++ b/KabylakeFspBinPkg/Include/FspsUpd.h
@@ -165,9 +165,16 @@ typedef struct {
**/
UINT8 ShowSpiController;
-/** Offset 0x0036
+/** Offset 0x0036 - Flash Configuration Lock Down
+ Enable/disable flash lock down. If platform decides to skip this
programming, it
+ must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
+ $EN_DIS
+**/
+ UINT8 SpiFlashCfgLockDown;
+
+/** Offset 0x0037
**/
- UINT8 UnusedUpdSpace0[2];
+ UINT8 UnusedUpdSpace0;
/** Offset 0x0038 - MicrocodeRegionBase
Memory Base of Microcode Updates
@@ -477,7 +484,7 @@ typedef struct {
/** Offset 0x020C - PCIe DeEmphasis control per root port
0: -6dB, 1(Default): -3.5dB
- 0:Disable, 2:L1
+ 0:-6dB, 1:-3.5dB
**/
UINT8 PegDeEmphasis[3];
@@ -2053,9 +2060,15 @@ typedef struct {
**/
UINT8 MeUnconfigIsValid;
-/** Offset 0x077A
+/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state
issues.
+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR
mailbox
+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA
rails.
+**/
+ UINT8 IslVrCmd;
+
+/** Offset 0x077B
**/
- UINT8 ReservedFspsUpd[6];
+ UINT8 ReservedFspsUpd[5];
} FSP_S_CONFIG;
/** Fsp S Test Configuration
@@ -2100,7 +2113,7 @@ typedef struct {
UINT8 DmiIot;
/** Offset 0x0789 - PEG Max Payload size per root port
- 0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B
+ 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
**/
UINT8 PegMaxPayload[3];
@@ -2513,25 +2526,25 @@ typedef struct {
/** Offset 0x07DA - Enable or Disable Package C-State Demotion
Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2:
Auto</b>
(Auto: Enabled for Skylake; Disabled for Kabylake)
- $EN_DIS
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 PkgCStateDemotion;
/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2:
Auto</b>
(Auto: Enabled for Skylake; Disabled for Kabylake)
- $EN_DIS
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 PkgCStateUnDemotion;
/** Offset 0x07DC - Enable or Disable CState-Pre wake
- Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
/** Offset 0x07DD - Enable or Disable TimedMwait Support.
- Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
@@ -2599,7 +2612,7 @@ typedef struct {
/** Offset 0x07E8 - Configuration for boot TDP selection
Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2:
TDP
- Up;0xFF : Deactivate
+ Up; 0xFF: Deactivate
0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate
**/
UINT8 ConfigTdpLevel;
@@ -2625,12 +2638,14 @@ typedef struct {
UINT16 StateRatio[40];
/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
- Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to
0x3FF
+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to
0x3FF,
+ Default is 0x4E, Server Platform is 0x4B
**/
UINT16 CstateLatencyControl0Irtl;
/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to
0x3FF
+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to
0x3FF,
+ Default is 0x76, Server Platform is 0x6B
**/
UINT16 CstateLatencyControl1Irtl;
@@ -2776,11 +2791,18 @@ typedef struct {
**/
UINT8 EightCoreRatioLimit;
-/** Offset 0x0888 - ReservedCpuPostMemTest
+/** Offset 0x0888 - Set Three Strike Counter Disable
+ False (default): Three Strike counter will be incremented and True: Prevents
Three
+ Strike counter from incrementing; <b>0: False</b>; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 ThreeStrikeCounterDisable;
+
+/** Offset 0x0889 - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
- UINT8 ReservedCpuPostMemTest[2];
+ UINT8 ReservedCpuPostMemTest[1];
/** Offset 0x088A - SgxSinitDataFromTpm
SgxSinitDataFromTpm default values
@@ -2916,7 +2938,7 @@ typedef struct {
UINT8 PchPmDisableEnergyReport;
/** Offset 0x0A2F - PCH Pm Pmc Read Disable
- When set to true, this bit disallows host reads to PMC XRAM.
+ Deprecated
$EN_DIS
**/
UINT8 PchPmPmcReadDisable;
diff --git a/KabylakeFspBinPkg/Include/MemInfoHob.h
b/KabylakeFspBinPkg/Include/MemInfoHob.h
index 2cd11f7..248b4d5 100644
--- a/KabylakeFspBinPkg/Include/MemInfoHob.h
+++ b/KabylakeFspBinPkg/Include/MemInfoHob.h
@@ -1,16 +1,32 @@
/** @file
- This file contains definitions required for creation of
- Memory S3 Save data, Memory Info data and Memory Platform
- data hobs.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available
under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Redistribution and use in source and binary forms, with or without
modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _MEM_INFO_HOB_H_
@@ -125,7 +141,7 @@ typedef struct {
#define MRC_DDR_TYPE_UNKNOWN 3
#endif
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
//
@@ -154,59 +170,69 @@ typedef struct {
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum
internal write to read command delay time for different bank groups.
} MRC_CH_TIMING;
+typedef struct {
+ UINT8 SG; ///< Number of tCK cycles between transactions in the same
bank group.
+ UINT8 DG; ///< Number of tCK cycles between transactions when
switching bank groups.
+ UINT8 DR; ///< Number of tCK cycles between transactions when
switching between Ranks (in the same DIMM).
+ UINT8 DD; ///< Number of tCK cycles between transactions when
switching between DIMMs.
+} MRC_TA_TIMING;
+
///
/// Memory SMBIOS & OC Memory Data Hob
///
typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the
definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3
is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this
DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType
information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType
information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth
information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing
information needed for SMBIOS structure creation.
+ UINT8 Status; ///< See MrcDimmStatus for the
definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3
is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this
DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType
information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType
information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth
information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing
information needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
- UINT8 Status; ///< Indicates whether this
channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that
exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output
characteristics.
+ UINT8 Status; ///< Indicates whether this
channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that
exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output
characteristics.
} CHANNEL_INFO;
typedef struct {
- UINT8 Status; ///< Indicates whether this
controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this
memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this
memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that
exist on the controller.
- CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel
level definitions.
+ UINT8 Status; ///< Indicates whether this
controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this
memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this
memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels
that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel
level definitions.
+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around
Timings
+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around
Timings
+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around
Timings
+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around
Timings
} CONTROLLER_INFO;
typedef struct {
- EFI_HOB_GUID_TYPE EfiHobGuidType;
UINT8 Revision;
- UINT16 DataWidth;
+ UINT16 DataWidth; ///< Data width, in bits, of this
memory device
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
- UINT8 DdrType; ///< DDR type: DDR3, DDR4, or
LPDDR3
- UINT32 Frequency; ///< The system's common memory
controller frequency in MT/s.
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or
LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of
the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock
speed to the memory device, in megahertz (MHz)
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
- UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK
value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; // If XMP capable
DIMMs are detected, this will indicate which XMP Profiles are common among all
DIMMs.
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK
value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable
DIMMs are detected, this will indicate which XMP Profiles are common among all
DIMMs.
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE_NUM];
@@ -239,6 +265,7 @@ typedef struct {
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
+
#pragma pack (pop)
#endif // _MEM_INFO_HOB_H_
--
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