diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig
index c344615..57be831 100644
--- a/src/mainboard/intel/leafhill/Kconfig
+++ b/src/mainboard/intel/leafhill/Kconfig
@@ -82,4 +82,8 @@ config FSP_M_CBFS
 	string
 	default "fspm.bin"
 
+config MAX_CPUS
+	int
+	default 4
+
 endif # BOARD_INTEL_LEAFHILL
diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc
index c3077e7..5921512 100644
--- a/src/mainboard/intel/leafhill/Makefile.inc
+++ b/src/mainboard/intel/leafhill/Makefile.inc
@@ -1,4 +1,7 @@
 bootblock-y += bootblock.c
 
 romstage-y += romstage.c
+romstage-y += gpio.c
+
 ramstage-y += mainboard.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h
index 18d130b..5cf07a6 100644
--- a/src/mainboard/intel/leafhill/brd_gpio.h
+++ b/src/mainboard/intel/leafhill/brd_gpio.h
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation. All Rights Reserved.
+ * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,37 +14,16 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/gpio.h>
-
-static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */
-	PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */
-	PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */
-	PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */
-
-	PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
-
-	/* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */
-	PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
-	/* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */
-	PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
+#ifndef _BRD_GPIO_H_
+#define _BRD_GPIO_H_
 
-	PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */
-	PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */
-	PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */
-	PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */
-	PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */
+#include <soc/gpio.h>
 
-	PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *brd_gpio_table(size_t *num);
+const struct pad_config *brd_early_gpio_table(size_t *num);
 
-	PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1),
-};
+#endif /* _BRD_GPIO_H_ */
diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd
index a91ba9a..8c6dda8 100644
--- a/src/mainboard/intel/leafhill/leafhill.16384.fmd
+++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd
@@ -2,13 +2,13 @@ FLASH 16M {
 	SI_DESC@0x0 0x1000
 	IFWI@0x1000 0x2ff000
 	FMAP@0x300000 0x800
-	COREBOOT(CBFS)@0x300800 0xc1d800
-	UNIFIED_MRC_CACHE@0xf1e000 0x21000 {
+	COREBOOT(CBFS)@0x300800 0xb9d800
+	UNIFIED_MRC_CACHE@0xe9e000 0x21000 {
 		RECOVERY_MRC_CACHE@0x0 0x10000
 		RW_MRC_CACHE@0x10000 0x10000
 		RW_VAR_MRC_CACHE@0x20000 0x1000
 	}
-	BIOS_UNUSABLE@0xf3f000 0x40000
-	DEVICE_EXTENSION@0xf7f000 0x7f000
+	BIOS_UNUSABLE@0xebf000 0x40000
+	DEVICE_EXTENSION@0xeff000 0x100000
 	UNUSED_HOLE@0xfff000 0x1000
 }
diff --git a/src/mainboard/intel/leafhill/mainboard.c b/src/mainboard/intel/leafhill/mainboard.c
index f7a2ef1..b05983d 100644
--- a/src/mainboard/intel/leafhill/mainboard.c
+++ b/src/mainboard/intel/leafhill/mainboard.c
@@ -14,10 +14,15 @@
  */
 
 #include <device/device.h>
+#include "brd_gpio.h"
 
 static void mainboard_init(void *chip_info)
 {
-	/* Nothing Here Yet */
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = brd_gpio_table(&num);
+	gpio_configure_pads(pads, num);
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c
index 5c784ba..d53e651 100644
--- a/src/mainboard/intel/leafhill/romstage.c
+++ b/src/mainboard/intel/leafhill/romstage.c
@@ -46,8 +46,12 @@ static const uint8_t Ch3_Bit_swizzling[] = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct pad_config *pads;
+	size_t num;
+
 	/* setup early gpio before memory */
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	pads = brd_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
 
 	/* DRAM Config settings */
 	memupd->FspmConfig.Package = 0x1;