awokd, could you please answer some questions: 1) From where you got that 0x06001119 microcode patch? Is it a trusted source of a microcode? (hope its directly from AMD)
2) Is there any way to determine that 0x06001119 is really the latest microcode? Or there could be more recent versions available? Best regards, Ivan Ivanov 2017-12-12 6:21 GMT+03:00 [email protected] <[email protected]>: > Congratulations for following through on the investigation :D > > I am not sure how to do a commit, but I hope you are able to find out as you > will have helped a lot of people. > > I am pleased with myself for noticing that the lack of microcode updates was > the issue - as the CPU is similar to a piledriver not a bulldozer it > requires microcode for IOMMU. > > I do not have the technical documents for that chipset and I do not know how > to change the PCI regs but I am sure the USB controllers support FLR > considering the nearly identical SR56xx chipsets usb controllers do - I will > look in to this further. > > > -- > coreboot mailing list: [email protected] > https://mail.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
