Hi Piotr,
This will give you layout file similar to: 00000000:00000fff fd
00400000:007fffff bios 00001000:003fffff me 00000000:00000fff
gbe
I got this as well. Zoran just told me offline that fd and gbe
seems to overlap. He also told me that the layout should be fd,
gbe, me and finally bios. Is the ifdtool output correct?
I also wonder about that. IMO there can be 2 things - incorrect
parsing of flash descriptor by ifdtool or incorrect values in flash
descriptor. This may be because this firmware doesn't have GbE
firmware. I wondered what will happen if we apply different
permissions to fd and gbe.
If you look at addresses bios is at the end. At least this layout
works. How to interpret overlapping regions I don't know.
With your tip to flash only the bios section I have some success. There
is debug output now on the serial console. It will hang eventually but
that might just be, that I use an too old FSP.
Then copy build/coreboot.rom and layout file to your RPi and
flash:
(rpi) $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32000
-l \ layout -i bios -w /tmp/coreboot.rom
Our container have default FSP from GitHub which is not the most
recent one. Latest you can obtain only through Intel RDC portal.
I suppose the one from GitHub is good enough though? I don't have
an RDC portal account.
Yes. But if you would like to complain to Intel for performance
related stuff they will say "please use recent one" and then you can
complain on correct one :)
Pretty bad job by Intel I'd say. Especially if the boss of OTC is
proclaiming that the MinnowBoard is blob free.
/me starts searching for working FSP.
Thanks,
Daniel
--
coreboot mailing list: [email protected]
https://mail.coreboot.org/mailman/listinfo/coreboot
