Hello, Thank you very much for the detailed reply. Vendor's BIOS contains few peripherals initialization. For example: PCIe enumeration, SATA controller, USB etc. In case of PCIe enumeration, the generation of PCIe (1,2,3) can be set. Should vendor supply code for this ? or any other information ? How can I write it from scratch ? Can Intel provide information on how to implement this initialization ?
Thank you, Zvika On Mon, Jun 18, 2018 at 11:22 AM Jose Trujillo via coreboot < [email protected]> wrote: > Hello Zvika: > 1.- Usually it is not necessary to change the CBFS size unless the > compiler complain of lack of space. > 2.- You should not worry about this setting to make your system to work. > 3.- You should not use FSP_PACKAGE_DEFAULT if your plan is to use SIO > because it will enable SOC internal COM1, instead (if your plan is to use > FSP) enable FSP and add a VGA bios bin manually.... (The use of FSP is > optional but I never tried without FSP). > 4.- You need to add them yourself, there are examples to follow in this > mail list. > Good luck! > J.Trujillo > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On June 18, 2018 6:24 AM, Zvi Vered <[email protected]> wrote: > > Hello, > I inspected the "Bayley Baay FSP-based CRB" sample in coreboot. after make > distclean I chose: > Mainboard vendor: Intel > Mainboard model: Bayley Bay FSP-based CRB > 1. The size of CBFS is: 0x200000. Is it a fix size or should I change it > according to my board (which is also bay trail) ? > 2. According to "dmidecode" I ran on my target, "Address: 0xE0000" > Should I set this address in coreboot configuration ? How ? > > 3. In this board default configuration, "Configure defaults for the Intel > FSP package" is not selected. Is it possible that this board does not use > Intel FSP at all ? > Under "Generic Drivers", "Use Intel firmware Support Package' is also not > selected. > > 4. Under "chipset", there is no option to set "Super I/O". Can you please > tell why ? > 5. I noticed that the minimum ROM size is 2MB. If I set 4MB, the size of > coreboot.rom is also 4MB. > > Thank you in advance, > Zvika > > > -- > coreboot mailing list: [email protected] > https://mail.coreboot.org/mailman/listinfo/coreboot
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