-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 On 06/21/2018 01:14 AM, Timothy Pearson wrote: > On 06/20/2018 09:13 PM, [email protected] wrote: >> https://www.phoronix.com/forums/forum/hardware/motherboards-chipsets/1021175-risc-v-sifive-freedom-unleahsed-540-soc-hifive-unleashed-board-added-to-coreboot > >> The board costs almost as much as a significantly faster and with much >> more features (IOMMU!) TALOS 2 Lite so I think it is not really worth >> buying right now for someone like me but I am still very curious about it. > >> - Unlike the usual crappy SOC products like this there is an available >> sexy expansion board which contains not one but two PCI-e slots and >> various other expansion options including SATA...which all really should >> have came standard. But unfortunately once you buy all the extras that >> make it usable you could have bought a very nice T2 setup so this is >> only for the die-hard hero developers and early adopters. (But I wish I >> had the cash for both!) > > >> My questions: > >> Is it possible to do normal stuff like browse the internet and watch a >> film via video acceleration if you pop in a decent graphics card? > >> Are there absolutely no binary blobs? Not even for the NIC? It is >> difficult to find NIC ASIC's that don't have blobs and with RISCV's >> unfortunate lack of an IOMMU this is a very big security issue for >> RISCV. At least with the TALOS 2 there is POWER-IOMMU to isolate it from >> doing anything evil and various people are working on a libre >> replacement which will benefit the entire libre community and anyone >> that likes cheap+good nics. > >> Whats the deal with SMM? What a shame they thought to add it. > > >> I really hope this succeeds and that they eventually add an IOMMU. > > > Their bootloader is a blob in ROM, for what it's worth. They also will > not release source for it [1]. I haven't looked further since that > alone is a dealbreaker for an "open" / auditable chip. > > [1] https://www.bunniestudios.com/blog/?p=5127 >
Correction: it's the pre-boot loader that's the problem. POWER neatly sidesteps that since the chip doesn't use any pre-reset code per se, and in fact goes through a lengthy process to reset all the latches as part of the open source boot code (see scan rings, etc.). I'd expect more, a *lot* more, from RISC-V to compensate for its lack of performance and other features. Seeing the only fabbed general purpose chip (AFAIK) be more closed than a closed-ISA competitor is not encouraging at this stage. Just my personal $0.02 here, not speaking for Raptor overall :) - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBCAAGBQJbK0NCAAoJEK+E3vEXDOFbUYgH/3w6mmD1BORMy7DB4vzjixFb 8LcJdAxFu6vsWqbl9Va2wvO11k8yqz9LOlk3c+YcDo3/uozlHyOGQrjKciSUFjtB vsu4p0v40bpHYOxMoictYbxLMJ7fFC1XNKjwEFclLpJ5y2YfuHx7p+lZ2KVrJca2 HNxIWjinYSuAcX6FFQCCeGPkHPcnFKfQz9vLQqAh8zZOOYIaGFT4NDTXlDu1W34/ +I5wzG1r7/o+uSQqLYE5zJQlru4nCbsU8H4SBEZvw+hNGTzdHrpVB6jrvj+z5QeI yFxUjOo6YvhVwn7gN9CRUJmazB5hJonCSxnDdsnO5i7631E7UXnYOjIozqoHi9U= =jstT -----END PGP SIGNATURE----- -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
