Hi, Lets do some speculation that some off the shelf DDR memory controller is used.
Maybe it could be same as the RockChip aka Denali High-Speed DDR PHY IP from Cadence? It has also some "interrupt status" bits and such and "bstlen" which sounds same as the few regs named as the documentation. Thanks Rudolf -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
