[resending, because I forgot to include [email protected]] > On Thu, Dec 20, 2018 at 11:56:17AM +0800, 王翔 wrote: > > I tried to adapt coreboot to HiFive-Unleashed and boot bbl with coreboot > > and run linux. > > My changes are as follows: > > > > https://github.com/hardenedlinux/coreboot-HiFiveUnleashed/tree/HiFive-Unleashed-Test-Change > > > > My code can run bbl, but it doesn't respond when bbl exits m-mode and > > enters linux. > > > > I use freedom-u-sdk to compile bbl. In order not to conflict with the > > coreboot memory address, execute the following command. > > riscv64-elf-objcopy --change-addresses 0x200000 work/riscv-pk/bbl > > ../coreboot/payload.elf > > > > I don't know what I missed, what should I do, I hope to get your help. > > You could try to change the base address in bbl/bbl.lds. This might > help, if for example bbl finds _payload_start with a LUI instruction > rather than a AUIPC instruction.
I have finally tested this. I used coreboot 4.8-2510-g75c6697322 (top of your HiFive-Unleashed-Test-Change branch), Linux 4.20, and bbl archive-1.9.1-132-ga02257a (current top of the master branch), with a patch in bbl/bbl.lds to change the base from 0x80000000 to 0x81000000: diff --git a/bbl/bbl.lds b/bbl/bbl.lds index 397cd3f..059d023 100644 --- a/bbl/bbl.lds +++ b/bbl/bbl.lds @@ -12,7 +12,7 @@ SECTIONS /*--------------------------------------------------------------------*/ /* Begining of code and text segment */ - . = 0x80000000; + . = 0x81000000; _ftext = .; .text : I get the following output: > coreboot-4.8-2510-g75c6697322 Fri Jan 4 04:27:37 UTC 2019 bootblock > starting... > Boot mode: 15 > CBFS: 'Master Header Locator' located CBFS at [20100:c00000) > CBFS: Locating 'fallback/romstage' > CBFS: Found @ offset 80 size 3745 > Hart 1 jumping to boot code at 0000000008020000, fdt: 0000000000010dc8 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 0 jumping to boot code at 0000000008020000, fdt: 0000000000010dc8 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 4 jumping to boot code at 0000000008020000, fdt: 0000000000010dc8 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 3 jumping to boot code at 0000000008020000, fdt: 0000000000010dc8 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 2 jumping to boot code at 0000000008020000, fdt: 0000000000010dc8 > *(uint32_t*)fdt: 0xedfe0dd0 > > > CBMEM:ot-4.8-2510-g75c6697322 Fri Jan 4 04:27:37 UTC 2019 romstage > starting... > IMD: root @ 000000027ffff000 254 entries. > IMD: root @ 000000027fffec00 62 entries. > CBFS: 'Master Header Locator' located CBFS at [20100:c00000) > CBFS: Locating 'fallback/DTB' > CBFS: Found @ offset 8fc0 size 29e4 > CBFS: 'Master Header Locator' located CBFS at [20100:c00000) > CBFS: Locating 'fallback/ramstage' > CBFS: Found @ offset 3800 size 53cb > Hart 0 jumping to boot code at 0000000080000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 1 jumping to boot code at 0000000080000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 4 jumping to boot code at 0000000080000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 3 jumping to boot code at 0000000080000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 2 jumping to boot code at 0000000080000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > > > coreboot-4.8-2510-g75c6697322 Fri Jan 4 04:27:37 UTC 2019 ramstage > starting... > BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 0 > BS: BS_DEV_INIT_CHIPS times (us): entry 1 run 0 exit 0 > Enumerating buses... > CPU_CLUSTER: 0 enabled > scan_bus: scanning of bus Root Device took 2054 usecs > done > BS: BS_DEV_ENUMERATE times (us): entry 0 run 9290 exit 0 > Allocating resources... > Reading resources... > CPU_CLUSTER: 0 missing read_resources > Done reading resources. > Setting resources... > Done setting resources. > Done allocating resources. > BS: BS_DEV_RESOURCES times (us): entry 0 run 16149 exit 0 > Enabling resources... > done. > BS: BS_DEV_ENABLE times (us): entry 0 run 2605 exit 0 > Initializing devices... > Root Device init ... > Root Device init finished in 1911 usecs > Devices initialized > BS: BS_DEV_INIT times (us): entry 0 run 9464 exit 0 > Finalize devices... > Devices finalized > BS: BS_POST_DEVICE times (us): entry 0 run 3473 exit 0 > BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0 > Writing coreboot table at 0x27ffd9000 > 0. 0000000080000000-0000000080011fff: RAMSTAGE > 1. 0000000080012000-000000008003ffff: RAM > 2. 0000000080040000-0000000080044fff: RAMSTAGE > 3. 0000000080045000-000000027ffd8fff: RAM > 4. 000000027ffd9000-000000027fffffff: CONFIGURATION TABLES > CBFS: 'Master Header Locator' located CBFS at [20100:c00000) > FMAP: Found "FLASH" version 1.1 at 20000. > FMAP: base = 0 size = c00000 #areas = 4 > Wrote coreboot table at: 000000027ffd9000, 0x158 bytes, checksum e28b > coreboot table: 368 bytes. > IMD ROOT 0. 000000027ffff000 00001000 > IMD SMALL 1. 000000027fffe000 00001000 > CONSOLE 2. 000000027ffde000 00020000 > Device Tree 3. 000000027ffdb000 000029e4 > COREBOOT 4. 000000027ffd9000 00002000 > IMD small region: > IMD ROOT 0. 000000027fffec00 00000400 > BS: BS_WRITE_TABLES times (us): entry 0 run 69804 exit 1 > CBFS: 'Master Header Locator' located CBFS at [20100:c00000) > CBFS: Locating 'fallback/payload' > CBFS: Found @ offset ba00 size 38b8ed > Checking segment from ROM address 0x000000002002bb38 > Checking segment from ROM address 0x000000002002bb54 > Checking segment from ROM address 0x000000002002bb70 > Checking segment from ROM address 0x000000002002bb8c > Loading segment from ROM address 0x000000002002bb38 > code (compression=1) > New segment dstaddr 0x0000000081000000 memsize 0x6af8 srcaddr > 0x000000002002bba8 filesize 0x401e > Loading Segment: addr: 0x0000000081000000 memsz: 0x0000000000006af8 filesz: > 0x000000000000401e > using LZMA > Loading segment from ROM address 0x000000002002bb54 > data (compression=1) > New segment dstaddr 0x0000000081007000 memsize 0xb080 srcaddr > 0x000000002002fbc6 filesize 0x65 > Loading Segment: addr: 0x0000000081007000 memsz: 0x000000000000b080 filesz: > 0x0000000000000065 > using LZMA > Clearing Segment: addr: 0x0000000081008065 memsz: 0x000000000000a01b > Loading segment from ROM address 0x000000002002bb70 > data (compression=1) > New segment dstaddr 0x0000000081200000 memsize 0x86b4cc srcaddr > 0x000000002002fc2b filesize 0x3877fa > Loading Segment: addr: 0x0000000081200000 memsz: 0x000000000086b4cc filesz: > 0x00000000003877fa > using LZMA > Loading segment from ROM address 0x000000002002bb8c > Entry Point 0x0000000081000000 > BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2904289 exit 0 > Jumping to boot code at 0000000081000000(000000027ffd9000) > Hart 0 jumping to boot code at 0000000081000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 2 jumping to boot code at 0000000081000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 3 jumping to boot code at 0000000081000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 1 jumping to boot code at 0000000081000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > Hart 4 jumping to boot code at 0000000081000000, fdt: 000000027ffdb000 > *(uint32_t*)fdt: 0xedfe0dd0 > bbl loader > [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x81200000 > [ 0.000000] Linux version 4.20.0 (jn@longitude) (gcc version 8.2.0 (Debian > 8.2.0-11)) #8 SMP Sun Jan 6 22:41:53 CET 2019 > [ 0.000000] printk: bootconsole [early0] enabled > [ 0.000000] initrd not found or empty - disabling initrd > [ 0.000000] Zone ranges: > [ 0.000000] DMA32 [mem 0x0000000081200000-0x00000000ffffffff] > [ 0.000000] Normal [mem 0x0000000100000000-0x000027ffffffffff] > [ 0.000000] Movable zone start for each node > [ 0.000000] Early memory node ranges > [ 0.000000] node 0: [mem 0x0000000081200000-0x000000027fffffff] > [ 0.000000] Initmem setup node 0 [mem > 0x0000000081200000-0x000000027fffffff] > [ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB) > [ 0.000000] CPU with hartid=0 has a non-okay status of "masked" > [ 0.000000] CPU with hartid=0 has a non-okay status of "masked" > [ 0.000000] elf_hwcap is 0x112d > [ 0.000000] percpu: Embedded 17 pages/cpu @(____ptrval____) s29464 r8192 > d31976 u69632 > [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063935 > [ 0.000000] Kernel command line: > [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 > bytes) > [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 > bytes) > [ 0.000000] Sorting __ex_table... > [ 0.000000] Memory: 8168540K/8370176K available (5509K kernel code, 336K > rwdata, 1760K rodata, 192K init, 806K bss, 201636K reserved, 0K cma-reserved) > [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 > [ 0.000000] rcu: Hierarchical RCU implementation. > [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. > [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 > jiffies. > [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 > [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 > [ 0.000000] plic: mapped 53 interrupts to 4 (out of 9) handlers. > [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff > max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns > [ 0.000000] Console: colour dummy device 80x25 > [ 0.004000] printk: console [tty0] enabled > [ 0.008000] printk: bootconsole [early0] disabled Linux doesn't boot all the way because Linux 4.20 doesn't have all the necessary drivers for the HiFive Unleashed. I built bbl with the following commands: mkdir build; cd build ../configure --host=riscv64-linux-gnu --with-payload=<path to Linux riscv build directory>/vmlinux && make -j1 make In coreboot, I selected the mainboard, configured the payload mode to M-mode, configured the image size to 12MiB, and added bbl.elf as the payload. Jonathan Neuschäfer
signature.asc
Description: PGP signature
_______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
