Hi Jonathan, On 13.02.19 08:31, Jonathan Zhang wrote: > Hi, I am working on porting coreboot to Skylake SP and OCP Tiogapass > with FSP 2.0. I have a strange issue that I hope to get some wisdom. > The boot hangs when executing this line "sub %ecx, %ebx" in > src/arch/x86/walkcbfs.S
I don't know what might cause it, but have two pointers: 1. I was wondering why you would have to look at CBFS from assembly at all. Do you have CONFIG_FSP_CAR set? Using the FSP CAR setup is probably not the best idea, as it is likely the least tested path. Better select a native coreboot solution instead, in case. 2. First idea that always jumps into mind when I see early instabili- ties: Do you have microcode updates *matching your CPU stepping* in your coreboot.rom? It might also be worth to check if the FIT table points correctly to them (64 bytes from the top of the .rom should be a pointer to the FIT, that should have an entry pointing to the updates). I don't know about Skylake, but generally, there may be steppings that need an update really early. Hope that helps, Nico _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
