Hi folks,
For some reason, gfx wont init on Sandybridge P8H61-M PRO with i5-2500T
on coreboot 4.9
Following a recommendation from Icon in coreboot IRC chat, the following
debug was added to check the value of reg16
diff ../core2/src/northbridge/intel/sandybridge/early_init.c
./src/northbridge/intel/sandybridge/early_init.c
86c86
<
---
>
102a103
> printk(BIOS_DEBUG, "%lx\n", (long)reg16);
The serial log shows
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019
romstage starting (log level: 7)...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
ffff
Graphics not supported by this CPU/chipset.
Back from sandybridge_early_initialization()
lspci with manufacturers BIOS and linux shows the display controller at
00:02.0 as 8086:0102 . There are no other display controllers connected
to the system.
Build log, defconfig, flash log and boot log are attached
Any pointers are greatly appreciated!
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019 romstage
starting (log level: 7)...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
ffff
Graphics not supported by this CPU/chipset.
Back from sandybridge_early_initialization()
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 16MB UMA
Starting native Platform init
FMAP: Found "FLASH" version 1.1 at 310000.
FMAP: base = ffc00000 size = 400000 #areas = 4
FMAP: area RW_MRC_CACHE found @ 300000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
SPD probe channel0, slot0
SPD probe channel0, slot1
SPD probe channel0, slot0
Row addr bits : 16
Column addr bits : 10
Number of ranks : 2
DIMM Capacity : 8192 MB
CAS latencies : 6 7 8 9
tCKmin : 1.500 ns
tAAmin : 13.125 ns
tWRmin : 15.000 ns
tRCDmin : 13.125 ns
tRRDmin : 6.000 ns
tRPmin : 13.125 ns
tRASmin : 36.000 ns
tRCmin : 49.125 ns
tRFCmin : 300.000 ns
tWTRmin : 7.500 ns
tRTPmin : 7.500 ns
tFAWmin : 30.000 ns
channel[0] rankmap = 0x3
SPD probe channel0, slot1
SPD probe channel1, slot0
SPD probe channel1, slot1
SPD probe channel1, slot0
SPD probe channel1, slot1
Starting SandyBridge RAM training (0).
Trying CAS 9, tCK 384.
Found compatible clock, CAS pair.
Selected DRAM frequency: 666 MHz
Selected CAS latency : 9T
PLL busy... done in 10 us
MCU frequency is set at : 666 MHz
Selected CWL latency : 7T
Selected tRCD : 9T
Selected tRP : 9T
Selected tRAS : 24T
Selected tWR : 10T
Selected tFAW : 20T
Selected tRRD : 4T
Selected tRTP : 5T
Selected tWTR : 5T
Selected tRFC : 201T
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 2
PCI(0, 0, 0)[bc] = 8a800000
PCI(0, 0, 0)[a8] = 74800000
PCI(0, 0, 0)[ac] = 2
PCI(0, 0, 0)[b8] = 80000000
PCI(0, 0, 0)[b0] = 80800000
PCI(0, 0, 0)[b4] = 80800000
PCI(0, 0, 0)[7c] = 7f
PCI(0, 0, 0)[70] = ff000000
PCI(0, 0, 0)[74] = 1
PCI(0, 0, 0)[78] = ff000c00
Done memory map
Done io registers
Done jedec reset
Done MRS commands
t123: 1912, 9120, 500
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : BUP Phase
ME: Power Management Event : Clean Moff->Mx wake
ME: Progress Phase State : Waiting for DID BIOS message
ME: FWS2: 0x101f01b6
ME: Bist in progress: 0x0
ME: ICC Status : 0x3
ME: Invoke MEBx : 0x0
ME: CPU replaced : 0x1
ME: MBP ready : 0x1
ME: MFS failure : 0x0
ME: Warm reset req : 0x1
ME: CPU repl valid : 0x1
ME: (Reserved) : 0x0
ME: FW update req : 0x0
ME: (Reserved) : 0x0
ME: Current state : 0x1f
ME: Current PM event: 0x0
ME: Progress code : 0x1
CPU was replaced & warm reset required...
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019 romstage
starting (log level: 7)...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
Back from sandybridge_early_initialization()
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 16MB UMA
Starting native Platform init
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019 romstage
starting (log level: 7)...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
Back from sandybridge_early_initialization()
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 16MB UMA
Starting native Platform init
FMAP: Found "FLASH" version 1.1 at 310000.
FMAP: base = ffc00000 size = 400000 #areas = 4
FMAP: area RW_MRC_CACHE found @ 300000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
SPD probe channel0, slot0
SPD probe channel0, slot1
SPD probe channel0, slot0
Row addr bits : 16
Column addr bits : 10
Number of ranks : 2
DIMM Capacity : 8192 MB
CAS latencies : 6 7 8 9
tCKmin : 1.500 ns
tAAmin : 13.125 ns
tWRmin : 15.000 ns
tRCDmin : 13.125 ns
tRRDmin : 6.000 ns
tRPmin : 13.125 ns
tRASmin : 36.000 ns
tRCmin : 49.125 ns
tRFCmin : 300.000 ns
tWTRmin : 7.500 ns
tRTPmin : 7.500 ns
tFAWmin : 30.000 ns
channel[0] rankmap = 0x3
SPD probe channel0, slot1
SPD probe channel1, slot0
SPD probe channel1, slot1
SPD probe channel1, slot0
SPD probe channel1, slot1
Starting SandyBridge RAM training (0).
Trying CAS 9, tCK 384.
Found compatible clock, CAS pair.
Selected DRAM frequency: 666 MHz
Selected CAS latency : 9T
PLL busy... done in 10 us
MCU frequency is set at : 666 MHz
Selected CWL latency : 7T
Selected tRCD : 9T
Selected tRP : 9T
Selected tRAS : 24T
Selected tWR : 10T
Selected tFAW : 20T
Selected tRRD : 4T
Selected tRTP : 5T
Selected tWTR : 5T
Selected tRFC : 201T
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 2
PCI(0, 0, 0)[bc] = 82a00000
PCI(0, 0, 0)[a8] = 7c600000
PCI(0, 0, 0)[ac] = 2
PCI(0, 0, 0)[b8] = 80000000
PCI(0, 0, 0)[b0] = 80a00000
PCI(0, 0, 0)[b4] = 80800000
PCI(0, 0, 0)[7c] = 7f
PCI(0, 0, 0)[70] = ff000000
PCI(0, 0, 0)[74] = 1
PCI(0, 0, 0)[78] = ff000c00
Done memory map
Done io registers
Done jedec reset
Done MRS commands
t123: 1912, 9120, 500
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : BUP Phase
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : Waiting for DID BIOS message
ME: FWS2: 0x161f0136
ME: Bist in progress: 0x0
ME: ICC Status : 0x3
ME: Invoke MEBx : 0x0
ME: CPU replaced : 0x1
ME: MBP ready : 0x1
ME: MFS failure : 0x0
ME: Warm reset req : 0x0
ME: CPU repl valid : 0x1
ME: (Reserved) : 0x0
ME: FW update req : 0x0
ME: (Reserved) : 0x0
ME: Current state : 0x1f
ME: Current PM event: 0x6
ME: Progress code : 0x1
Full training required
PASSED! Tell ME that DRAM is ready
ME: FWS2: 0x162c0136
ME: Bist in progress: 0x0
ME: ICC Status : 0x3
ME: Invoke MEBx : 0x0
ME: CPU replaced : 0x1
ME: MBP ready : 0x1
ME: MFS failure : 0x0
ME: Warm reset req : 0x0
ME: CPU repl valid : 0x1
ME: (Reserved) : 0x0
ME: FW update req : 0x0
ME: (Reserved) : 0x0
ME: Current state : 0x2c
ME: Current PM event: 0x6
ME: Progress code : 0x1
ME: Requested BIOS Action: Continue to boot
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : BUP Phase
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : 0x50
memcfg DDR3 ref clock 133 MHz
memcfg DDR3 clock 1330 MHz
memcfg channel assignment: A: 0, B 1, C 2
memcfg channel[0] config (00620020):
ECC inactive
enhanced interleave mode on
rank interleave on
DIMMA 8192 MB width x8 dual rank, selected
DIMMB 0 MB width x8 single rank
memcfg channel[1] config (00000000):
ECC inactive
enhanced interleave mode off
rank interleave off
DIMMA 0 MB width x8 single rank, selected
DIMMB 0 MB width x8 single rank
CBMEM:
IMD: root @ 7ffff000 254 entries.
IMD: root @ 7fffec00 62 entries.
External stage cache:
IMD: root @ 803ff000 254 entries.
IMD: root @ 803fec00 62 entries.
CBMEM entry for DIMM info: 0x7fffea40
MTRR Range: Start=ffc00000 End=0 (Size 400000)
MTRR Range: Start=0 End=1000000 (Size 1000000)
MTRR Range: Start=7f800000 End=80000000 (Size 800000)
MTRR Range: Start=80000000 End=80800000 (Size 800000)
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset 33400 size 3d74
Decompressing stage fallback/postcar @ 0x7ffcefc0 (32336 bytes)
Loading module at 7ffcf000 with entry 7ffcf000. filesize: 0x3b50 memsize: 0x7e10
Processing 114 relocs. Offset value of 0x7dfcf000
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019 postcar
starting (log level: 7)...
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 1a080 size 18a76
Decompressing stage fallback/ramstage @ 0x7ff84fc0 (298072 bytes)
Loading module at 7ff85000 with entry 7ff85000. filesize: 0x33750 memsize:
0x48c18
Processing 3476 relocs. Offset value of 0x7f185000
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019 ramstage
starting (log level: 7)...
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
Enumerating buses...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0100] enabled
PCI: 00:01.0 [8086/0101] enabled
PCI: 00:02.0 [8086/0102] enabled
PCI: 00:16.0 [8086/1c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.3: Disabling device
PCI: 00:19.0: Disabling device
PCI: 00:1a.0 [8086/1c2d] enabled
PCI: 00:1b.0 [8086/1c20] enabled
PCI: 00:1c.0 [8086/1c10] enabled
PCI: 00:1c.1 [8086/1c12] enabled
PCI: 00:1c.2 [8086/1c14] enabled
PCI: 00:1c.3 [8086/1c16] enabled
PCI: 00:1c.4 [8086/1c18] enabled
PCI: 00:1c.5 [8086/1c1a] enabled
PCI: 00:1c.6: Disabling device
PCI: 00:1c.7: Disabling device
PCI: 00:1d.0 [8086/1c26] enabled
PCI: 00:1e.0: Disabling device
PCI: 00:1e.0 [8086/244e] disabled No operations
PCI: 00:1f.0 [8086/1c5c] enabled
PCI: 00:1f.2 [8086/1c00] enabled
PCI: 00:1f.3 [8086/1c22] enabled
PCI: 00:1f.5: Disabling device
PCI: 00:1f.5 [8086/1c08] disabled No operations
PCI: 00:1f.6: Disabling device
PCI: 00:1f.6 [8086/1c24] disabled No operations
PCI: Leftover static devices:
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:1c.6
PCI: 00:1c.7
PCI: Check your devicetree.cb.
PCI: pci_scan_bus for bus 01
scan_bus: scanning of bus PCI: 00:01.0 took 2619 usecs
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:1c.0 took 2647 usecs
PCI: pci_scan_bus for bus 03
scan_bus: scanning of bus PCI: 00:1c.1 took 2648 usecs
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [10ec/8168] enabled
Enabling Common Clock Configuration
ASPM: Enabled L1
Failed to enable LTR for dev = PCI: 04:00.0
scan_bus: scanning of bus PCI: 00:1c.2 took 14429 usecs
PCI: pci_scan_bus for bus 05
PCI: 05:00.0 [1b21/1042] enabled
Enabling Common Clock Configuration
ASPM: Enabled None
Failed to enable LTR for dev = PCI: 05:00.0
scan_bus: scanning of bus PCI: 00:1c.3 took 14628 usecs
PCI: pci_scan_bus for bus 06
scan_bus: scanning of bus PCI: 00:1c.4 took 2648 usecs
PCI: pci_scan_bus for bus 07
Disabling ASPM for PCI: 07:00.0 [1b21/0611]
PCI: 07:00.0 [1b21/0611] enabled
Enabling Common Clock Configuration
Failed to enable LTR for dev = PCI: 07:00.0
scan_bus: scanning of bus PCI: 00:1c.5 took 16866 usecs
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
PNP: 002e.b enabled
PNP: 002e.d enabled
PNP: 002e.e disabled
PNP: 002e.f enabled
PNP: 002e.14 enabled
PNP: 002e.16 enabled
PNP: 002e.17 enabled
PNP: 002e.108 enabled
PNP: 002e.109 enabled
PNP: 002e.209 enabled
PNP: 002e.309 enabled
PNP: 002e.409 enabled
PNP: 002e.509 enabled
PNP: 002e.609 enabled
PNP: 002e.709 enabled
PNP: 002e.107 enabled
PNP: 002e.208 enabled
scan_bus: scanning of bus PCI: 00:1f.0 took 52448 usecs
scan_bus: scanning of bus PCI: 00:1f.3 took 1 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 256423 usecs
scan_bus: scanning of bus Root Device took 265463 usecs
done
FMAP: Found "FLASH" version 1.1 at 310000.
FMAP: base = ffc00000 size = 400000 #areas = 4
FMAP: area RW_MRC_CACHE found @ 300000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
Manufacturer: ef
SF: Detected W25Q32_V with sector size 0x1000, total 0x400000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
BS: BS_DEV_ENUMERATE times (us): entry 0 run 272878 exit 36852
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
Done reading resources.
skipping PNP: 002e.1@f0 fixed resource, size=0!
skipping PNP: 002e.a@e5 fixed resource, size=0!
skipping PNP: 002e.a@e6 fixed resource, size=0!
skipping PNP: 002e.a@e7 fixed resource, size=0!
skipping PNP: 002e.a@f0 fixed resource, size=0!
skipping PNP: 002e.a@f2 fixed resource, size=0!
skipping PNP: 002e.f@f0 fixed resource, size=0!
skipping PNP: 002e.16@30 fixed resource, size=0!
skipping PNP: 002e.17@e0 fixed resource, size=0!
skipping PNP: 002e.17@e1 fixed resource, size=0!
skipping PNP: 002e.17@e2 fixed resource, size=0!
skipping PNP: 002e.17@e3 fixed resource, size=0!
skipping PNP: 002e.17@e5 fixed resource, size=0!
Setting resources...
TOUUD 0x27c600000 TOLUD 0x82a00000 TOM 0x200000000
MEBASE 0x1ff000000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0x80000000 size 8M
Available memory below 4GB: 2048M
Available memory above 4GB: 6086M
PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
01 io
PCI: 00:01.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
01 prefmem
PCI: 00:01.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
01 mem
PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c
prefmem64
PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
PCI: 00:16.0 10 <- [0x00e0708000 - 0x00e070800f] size 0x00000010 gran 0x04 mem64
PCI: 00:1a.0 10 <- [0x00e0705000 - 0x00e07053ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00e0700000 - 0x00e0703fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
02 io
PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
02 prefmem
PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
02 mem
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
03 io
PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
03 prefmem
PCI: 00:1c.1 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
03 mem
PCI: 00:1c.2 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus
04 io
PCI: 00:1c.2 24 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus
04 prefmem
PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
04 mem
PCI: 04:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 04:00.0 18 <- [0x00e0404000 - 0x00e0404fff] size 0x00001000 gran 0x0c
prefmem64
PCI: 04:00.0 20 <- [0x00e0400000 - 0x00e0403fff] size 0x00004000 gran 0x0e
prefmem64
PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
05 io
PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
05 prefmem
PCI: 00:1c.3 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus
05 mem
PCI: 05:00.0 10 <- [0x00e0500000 - 0x00e0507fff] size 0x00008000 gran 0x0f mem64
PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
06 io
PCI: 00:1c.4 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
06 prefmem
PCI: 00:1c.4 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
06 mem
PCI: 00:1c.5 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus
07 io
PCI: 00:1c.5 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus
07 prefmem
PCI: 00:1c.5 20 <- [0x00e0600000 - 0x00e06fffff] size 0x00100000 gran 0x14 bus
07 mem
PCI: 07:00.0 10 <- [0x0000002010 - 0x0000002017] size 0x00000008 gran 0x03 io
PCI: 07:00.0 14 <- [0x0000002020 - 0x0000002023] size 0x00000004 gran 0x02 io
PCI: 07:00.0 18 <- [0x0000002018 - 0x000000201f] size 0x00000008 gran 0x03 io
PCI: 07:00.0 1c <- [0x0000002024 - 0x0000002027] size 0x00000004 gran 0x02 io
PCI: 07:00.0 20 <- [0x0000002000 - 0x000000200f] size 0x00000010 gran 0x04 io
PCI: 07:00.0 24 <- [0x00e0600000 - 0x00e06001ff] size 0x00000200 gran 0x09 mem
PCI: 00:1d.0 10 <- [0x00e0706000 - 0x00e07063ff] size 0x00000400 gran 0x0a mem
PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
PNP: 002e.1 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
PNP: 002e.1 f0 <- [0x000000003c - 0x000000003b] size 0x00000000 gran 0x00 irq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.a e5 <- [0x0000000006 - 0x0000000005] size 0x00000000 gran 0x00 irq
PNP: 002e.a e6 <- [0x000000000c - 0x000000000b] size 0x00000000 gran 0x00 irq
PNP: 002e.a e7 <- [0x0000000011 - 0x0000000010] size 0x00000000 gran 0x00 irq
PNP: 002e.a f0 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq
PNP: 002e.a f2 <- [0x000000005d - 0x000000005c] size 0x00000000 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
PNP: 002e.b 62 <- [0x0000000200 - 0x0000000201] size 0x00000002 gran 0x01 io
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
PNP: 002e.f f0 <- [0x000000009d - 0x000000009c] size 0x00000000 gran 0x00 irq
PNP: 002e.16 30 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 io
PNP: 002e.17 e0 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq
PNP: 002e.17 e1 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq
PNP: 002e.17 e2 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq
PNP: 002e.17 e3 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq
PNP: 002e.17 e5 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq
PCI: 00:1f.2 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00e0704000 - 0x00e07047ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00e0707000 - 0x00e07070ff] size 0x00000100 gran 0x08 mem64
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 605460 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/0100
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 subsystem <- 8086/0101
PCI: 00:01.0 cmd <- 00
PCI: 00:02.0 subsystem <- 8086/0102
PCI: 00:02.0 cmd <- 03
PCI: 00:16.0 subsystem <- 8086/1c3a
PCI: 00:16.0 cmd <- 02
PCI: 00:1a.0 subsystem <- 8086/1c2d
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 8086/1c20
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 8086/1c10
PCI: 00:1c.0 cmd <- 100
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 subsystem <- 8086/1c12
PCI: 00:1c.1 cmd <- 100
PCI: 00:1c.2 bridge ctrl <- 0003
PCI: 00:1c.2 subsystem <- 8086/1c14
PCI: 00:1c.2 cmd <- 107
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 subsystem <- 8086/1c16
PCI: 00:1c.3 cmd <- 106
PCI: 00:1c.4 bridge ctrl <- 0003
PCI: 00:1c.4 subsystem <- 8086/1c18
PCI: 00:1c.4 cmd <- 100
PCI: 00:1c.5 bridge ctrl <- 0003
PCI: 00:1c.5 subsystem <- 8086/1c1a
PCI: 00:1c.5 cmd <- 107
PCI: 00:1d.0 subsystem <- 8086/1c26
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 8086/1c5c
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 8086/1c02
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 8086/1c22
PCI: 00:1f.3 cmd <- 103
PCI: 04:00.0 cmd <- 03
PCI: 05:00.0 cmd <- 02
PCI: 07:00.0 cmd <- 03
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 117250 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 1919 usecs
CPU_CLUSTER: 0 init ...
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000027c600000 size 0x17c600000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 4/4.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU has 4 cores, 4 threads enabled.
Setting up SMI for CPU
Will perform SMM setup.
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 13c00 size 6400
microcode: sig=0x206a7 pf=0x2 revision=0x2e
CPU: Intel(R) Core(TM) i5-2500T CPU @ 2.30GHz.
Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 3 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...done.
Waiting for 2nd SIPI to complete...done.
AP: slot 1 apic_id 2.
AP: slot 3 apic_id 4.
AP: slot 2 apic_id 6.
Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
Processing 13 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 00038000. Will call 7ffa20cd(00000000)
Installing SMM handler to 0x80000000
Loading module at 80010000 with entry 80010112. filesize: 0x1048 memsize: 0x5068
Processing 40 relocs. Offset value of 0x80010000
Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8
Processing 13 relocs. Offset value of 0x80008000
SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 80007800 rel16 0x07fd
SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd
SMM Module: stub loaded at 80008000. Will call 80010112(00000000)
Initializing Southbridge SMI...
New SMBASE 0x80000000
In relocation handler: cpu 0
New SMBASE=0x80000000 IEDBASE=0x80400000
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
New SMBASE 0x7ffff800
In relocation handler: cpu 2
New SMBASE=0x7ffff800 IEDBASE=0x80400000
microcode: Update skipped, already up-to-date
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
New SMBASE 0x7ffff400
In relocation handler: cpu 3
New SMBASE=0x7ffff400 IEDBASE=0x80400000
microcode: Update skipped, already up-to-date
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
New SMBASE 0x7ffffc00
In relocation handler: cpu 1
New SMBASE=0x7ffffc00 IEDBASE=0x80400000
microcode: Update skipped, already up-to-date
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
Initializing CPU #0
CPU: vendor Intel device 206a7
CPU: family 06, model 2a, stepping 07
Enabling cache
CPU: Intel(R) Core(TM) i5-2500T CPU @ 2.30GHz.
CPU: platform id 1
CPU: cpuid(1) 0x206a7
CPU: AES supported
CPU: TXT supported
CPU: VT supported
Setting up local APIC... apic_id: 0x00 done.
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2300
Turbo is available but hidden
Turbo has been enabled
CPU #0 initialized
Initializing CPU #3
Initializing CPU #1
CPU: vendor Intel device 206a7
CPU: family 06, model 2a, stepping 07
Initializing CPU #2
CPU: vendor Intel device 206a7
CPU: family 06, model 2a, stepping 07
Enabling cache
Enabling cache
CPU: vendor Intel device 206a7
CPU: family 06, model 2a, stepping 07
CPU: Intel(R) Core(TM) i5-2500T CPU @ 2.30GHz.
CPU: Intel(R) Core(TM) i5-2500T CPU @ 2.30GHz.
Enabling cache
CPU: platform id 1
CPU: Intel(R) Core(TM) i5-2500T CPU @ 2.30GHz.
CPU: cpuid(1) 0x206a7
CPU: platform id 1
CPU: AES supported
CPU: TXT supported
CPU: VT supported
CPU: cpuid(1) 0x206a7
CPU: platform id 1
Setting up local APIC...CPU: cpuid(1) 0x206a7
apic_id: 0x02 done.
CPU: AES supported
CPU: TXT supported
CPU: VT supported
CPU: AES supported
CPU: TXT supported
CPU: VT supported
VMX status: enabled
Setting up local APIC...IA32_FEATURE_CONTROL status: locked
apic_id: 0x04 done.
model_x06ax: energy policy set to 6
VMX status: enabled
model_x06ax: frequency set to 2300
IA32_FEATURE_CONTROL status: locked
Setting up local APIC...CPU #1 initialized
apic_id: 0x06 done.
model_x06ax: energy policy set to 6
VMX status: enabled
model_x06ax: frequency set to 2300
CPU #3 initialized
IA32_FEATURE_CONTROL status: locked
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 2300
CPU #2 initialized
bsp_do_flight_plan done after 318 msecs.
Initializing southbridge SMI...
SMI_STS:
GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1
GPI0
TCO_STS:
Locking SMM.
CPU_CLUSTER: 0 init finished in 527126 usecs
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling Device 4.
Disabling PEG60.
Disabling Device 7.
Set BIOS_RESET_CPL
CPU TDP: 45 Watts
PCI: 00:00.0 init finished in 14786 usecs
PCI: 00:01.0 init ...
PCI: 00:01.0 init finished in 2004 usecs
PCI: 00:02.0 init ...
GT Power Management Init
SNB GT1 Power Meter Weights
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 10613 usecs
PCI: 00:16.0 init ...
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : YES
ME: Manufacturing Mode : YES
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : Host Communication
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : Host communication established
ME: BIOS path: Normal
ME: Extend SHA-256:
4e84181ebfd078b12ba58d8811007b7eeefa420b40e59b4a46d82f86922a0a06
ME: response is not complete
ME: GET FW VERSION message failed
ME: response is not complete
ME: GET FWCAPS message failed
PCI: 00:16.0 init finished in 68473 usecs
PCI: 00:1a.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 5243 usecs
PCI: 00:1b.0 init ...
Azalia: base = e0700000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862805
Azalia: verb_size: 16
Azalia: verb loaded.
Azalia: Initializing codec #0
Azalia: codec viddid: 10ec0887
Azalia: verb_size: 60
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 30395 usecs
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 4708 usecs
PCI: 00:1c.1 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.1 init finished in 4708 usecs
PCI: 00:1c.2 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.2 init finished in 4707 usecs
PCI: 00:1c.3 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.3 init finished in 4708 usecs
PCI: 00:1c.4 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.4 init finished in 4708 usecs
PCI: 00:1c.5 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.5 init finished in 4708 usecs
PCI: 00:1d.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 5246 usecs
PCI: 00:1f.0 init ...
pch: lpc_init
PCH: detected H61, device id: 0x1c5c, rev id 0x5
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
Set power off after power failure.
NMI sources disabled.
CougarPoint PM init
RTC: failed = 0x0
RTC Init
Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 30971 usecs
PCI: 00:1f.2 init ...
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: e0704000
PCI: 00:1f.2 init finished in 8263 usecs
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 2008 usecs
PCI: 04:00.0 init ...
PCI: 04:00.0 init finished in 2006 usecs
PCI: 05:00.0 init ...
PCI: 05:00.0 init finished in 2003 usecs
PNP: 002e.1 init ...
PNP: 002e.1 init finished in 1913 usecs
PNP: 002e.2 init ...
PNP: 002e.2 init finished in 1915 usecs
PNP: 002e.5 init ...
PNP: 002e.5 init finished in 1913 usecs
PNP: 002e.a init ...
PNP: 002e.a init finished in 1915 usecs
PNP: 002e.b init ...
PNP: 002e.b init finished in 1917 usecs
PNP: 002e.d init ...
PNP: 002e.d init finished in 1916 usecs
PNP: 002e.f init ...
PNP: 002e.f init finished in 1914 usecs
PNP: 002e.14 init ...
PNP: 002e.14 init finished in 2003 usecs
PNP: 002e.16 init ...
PNP: 002e.16 init finished in 2003 usecs
PNP: 002e.17 init ...
PNP: 002e.17 init finished in 2003 usecs
PNP: 002e.108 init ...
PNP: 002e.108 init finished in 2091 usecs
PNP: 002e.109 init ...
PNP: 002e.109 init finished in 2089 usecs
PNP: 002e.209 init ...
PNP: 002e.209 init finished in 2089 usecs
PNP: 002e.309 init ...
PNP: 002e.309 init finished in 2088 usecs
PNP: 002e.409 init ...
PNP: 002e.409 init finished in 2090 usecs
PNP: 002e.509 init ...
PNP: 002e.509 init finished in 2088 usecs
PNP: 002e.609 init ...
PNP: 002e.609 init finished in 2089 usecs
PNP: 002e.709 init ...
PNP: 002e.709 init finished in 2089 usecs
PNP: 002e.107 init ...
PNP: 002e.107 init finished in 2088 usecs
PNP: 002e.208 init ...
PNP: 002e.208 init finished in 2088 usecs
Devices initialized
BS: BS_DEV_INIT times (us): entry 6 run 930556 exit 0
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 5290 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 371c0 size 2607
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7ff48000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * FADT
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Generating ACPI PIRQ entries
Found 1 CPU(s) with 4 core(s) each.
PSS: 2301MHz power 45000 control 0x2100 status 0x2100
PSS: 2300MHz power 45000 control 0x1700 status 0x1700
PSS: 2000MHz power 37775 control 0x1400 status 0x1400
PSS: 1800MHz power 33184 control 0x1200 status 0x1200
PSS: 1600MHz power 28804 control 0x1000 status 0x1000
PSS: 2301MHz power 45000 control 0x2100 status 0x2100
PSS: 2300MHz power 45000 control 0x1700 status 0x1700
PSS: 2000MHz power 37775 control 0x1400 status 0x1400
PSS: 1800MHz power 33184 control 0x1200 status 0x1200
PSS: 1600MHz power 28804 control 0x1000 status 0x1000
PSS: 2301MHz power 45000 control 0x2100 status 0x2100
PSS: 2300MHz power 45000 control 0x1700 status 0x1700
PSS: 2000MHz power 37775 control 0x1400 status 0x1400
PSS: 1800MHz power 33184 control 0x1200 status 0x1200
PSS: 1600MHz power 28804 control 0x1000 status 0x1000
PSS: 2301MHz power 45000 control 0x2100 status 0x2100
PSS: 2300MHz power 45000 control 0x1700 status 0x1700
PSS: 2000MHz power 37775 control 0x1400 status 0x1400
PSS: 1800MHz power 33184 control 0x1200 status 0x1200
PSS: 1600MHz power 28804 control 0x1000 status 0x1000
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * MADT
ACPI: added table 4/32, length now 52
current = 7ff4c190
ACPI: * DMAR
ACPI: added table 5/32, length now 56
current = 7ff4c260
ACPI: * HPET
ACPI: added table 6/32, length now 60
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'vbt.bin'
CBFS: 'vbt.bin' not found.
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'pci8086,0102.rom'
CBFS: 'pci8086,0102.rom' not found.
CBFS: 'Master Header Locator' located CBFS at [310200:400000)
CBFS: Locating 'pci8086,0106.rom'
$ make
Skipping submodule '3rdparty/blobs'
Skipping submodule '3rdparty/fsp'
#
# configuration written to /home/xxx/bios/coreboot/.config
#
CC bootblock/mainboard/asus/p8h61-m_pro/static.o
CC bootblock/arch/x86/boot.o
GEN generated/bootblock.ld
CP bootblock/arch/x86/bootblock.ld
ROMCC generated/bootblock.inc
CC bootblock/arch/x86/bootblock_romcc.o
CC bootblock/arch/x86/cf9_reset.o
CC bootblock/arch/x86/cpu_common.o
CC bootblock/arch/x86/id.o
CC bootblock/arch/x86/memcpy.o
CC bootblock/arch/x86/memset.o
CC bootblock/arch/x86/mmap_boot.o
CC bootblock/arch/x86/timestamp.o
CC bootblock/arch/x86/walkcbfs.o
CC bootblock/commonlib/cbfs.o
CC bootblock/commonlib/iobuf.o
CC bootblock/commonlib/lz4_wrapper.o
CC bootblock/commonlib/mem_pool.o
CC bootblock/commonlib/region.o
CC bootblock/console/die.o
CC bootblock/console/post.o
CC bootblock/console/vsprintf.o
CC bootblock/console/vtxprintf.o
CC bootblock/cpu/x86/lapic/boot_cpu.o
CC bootblock/cpu/x86/mtrr/debug.o
CC bootblock/cpu/x86/mtrr/earlymtrr.o
CC bootblock/cpu/x86/pae/pgtbl.o
CC bootblock/cpu/x86/tsc/delay_tsc.o
CC bootblock/device/device_const.o
CC bootblock/device/i2c.o
CC bootblock/device/pci_early.o
CC bootblock/drivers/pc80/rtc/mc146818rtc.o
CC bootblock/drivers/pc80/rtc/mc146818rtc_boot.o
CC bootblock/drivers/spi/adesto.o
CC bootblock/drivers/spi/amic.o
CC bootblock/drivers/spi/atmel.o
CC bootblock/drivers/spi/bitbang.o
CC bootblock/drivers/spi/eon.o
CC bootblock/drivers/spi/gigadevice.o
CC bootblock/drivers/spi/macronix.o
CC bootblock/drivers/spi/spansion.o
CC bootblock/drivers/spi/spi-generic.o
CC bootblock/drivers/spi/spi_flash.o
CC bootblock/drivers/spi/sst.o
CC bootblock/drivers/spi/stmicro.o
CC bootblock/drivers/spi/winbond.o
CC bootblock/drivers/uart/uart8250io.o
CC bootblock/drivers/uart/util.o
CC bootblock/lib/boot_device.o
CC bootblock/lib/bootmode.o
FMAP build/util/cbfstool/fmaptool -h build/fmap_config.h
build/fmap.fmd build/fmap.fmap
SUCCESS: Wrote 224 bytes to file 'build/fmap.fmap' (and generated header)
The sections containing CBFSes are: COREBOOT
CC bootblock/lib/cbfs.o
CC bootblock/lib/cbmem_console.o
CC bootblock/lib/delay.o
CC bootblock/lib/fmap.o
CC bootblock/lib/gcc.o
CC bootblock/lib/halt.o
CC bootblock/lib/hexdump.o
CC bootblock/lib/libgcc.o
CC bootblock/lib/memchr.o
CC bootblock/lib/memcmp.o
CC bootblock/lib/prog_loaders.o
CC bootblock/lib/prog_ops.o
CC bootblock/lib/reset.o
CC bootblock/lib/timestamp.o
CC bootblock/lib/version.o
CC bootblock/southbridge/intel/common/reset.o
CC bootblock/superio/nuvoton/common/early_serial.o
LINK cbfs/fallback/bootblock.debug
OBJCOPY cbfs/fallback/bootblock.elf
OBJCOPY bootblock.raw.elf
OBJCOPY bootblock.raw.bin
CC romstage/mainboard/asus/p8h61-m_pro/static.o
CC romstage/arch/x86/acpi_s3.o
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/cbfs_and_run.o
CC romstage/arch/x86/cbmem.o
CC romstage/arch/x86/cf9_reset.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/arch/x86/timestamp.o
CC romstage/arch/x86/walkcbfs.o
CC romstage/commonlib/cbfs.o
CC romstage/commonlib/iobuf.o
CC romstage/commonlib/lz4_wrapper.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vsprintf.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/intel/model_206ax/common.o
CC romstage/cpu/intel/model_206ax/stage_cache.o
CC romstage/cpu/intel/model_206ax/tsc_freq.o
CC romstage/cpu/x86/lapic/boot_cpu.o
CC romstage/cpu/x86/mtrr/debug.o
CC romstage/cpu/x86/mtrr/earlymtrr.o
CC romstage/cpu/x86/pae/pgtbl.o
CC romstage/cpu/x86/tsc/delay_tsc.o
CC romstage/device/device_const.o
CC romstage/device/dram/ddr2.o
CC romstage/device/dram/ddr3.o
CC romstage/device/i2c.o
CC romstage/device/pci_early.o
CC romstage/drivers/mrc_cache/mrc_cache.o
CC romstage/drivers/pc80/rtc/mc146818rtc.o
CC romstage/drivers/spi/adesto.o
CC romstage/drivers/spi/amic.o
CC romstage/drivers/spi/atmel.o
CC romstage/drivers/spi/bitbang.o
CC romstage/drivers/spi/eon.o
CC romstage/drivers/spi/gigadevice.o
CC romstage/drivers/spi/macronix.o
CC romstage/drivers/spi/spansion.o
CC romstage/drivers/spi/spi-generic.o
CC romstage/drivers/spi/spi_flash.o
CC romstage/drivers/spi/sst.o
CC romstage/drivers/spi/stmicro.o
CC romstage/drivers/spi/winbond.o
CC romstage/drivers/uart/uart8250io.o
CC romstage/drivers/uart/util.o
CC romstage/lib/boot_device.o
CC romstage/lib/bootmode.o
CC romstage/lib/cbfs.o
CC romstage/lib/cbmem_common.o
CC romstage/lib/cbmem_console.o
CC romstage/lib/compute_ip_checksum.o
CC romstage/lib/delay.o
CC romstage/lib/ext_stage_cache.o
CC romstage/lib/fmap.o
CC romstage/lib/gcc.o
CC romstage/lib/halt.o
CC romstage/lib/hexdump.o
CC romstage/lib/imd.o
CC romstage/lib/imd_cbmem.o
CC romstage/lib/libgcc.o
CC romstage/lib/lzma.o
CC romstage/lib/lzmadecode.o
CC romstage/lib/memchr.o
CC romstage/lib/memcmp.o
CC romstage/lib/memrange.o
CC romstage/lib/prog_loaders.o
CC romstage/lib/prog_ops.o
CP romstage/lib/program.ld
CC romstage/lib/ramtest.o
CC romstage/lib/region_file.o
CC romstage/lib/reset.o
CC romstage/lib/rmodule.o
CC romstage/lib/romstage_handoff.o
CC romstage/lib/romstage_stack.o
CC romstage/lib/selfboot.o
CC romstage/lib/spd_bin.o
CC romstage/lib/stack.o
CC romstage/lib/timestamp.o
CC romstage/lib/version.o
CC romstage/mainboard/asus/p8h61-m_pro/gpio.o
CC romstage/mainboard/asus/p8h61-m_pro/romstage.o
CC romstage/northbridge/intel/sandybridge/common.o
CC romstage/northbridge/intel/sandybridge/early_init.o
CC romstage/northbridge/intel/sandybridge/iommu.o
CC romstage/northbridge/intel/sandybridge/ram_calc.o
CC romstage/northbridge/intel/sandybridge/raminit.o
CC romstage/northbridge/intel/sandybridge/raminit_common.o
CC romstage/northbridge/intel/sandybridge/raminit_ivy.o
CC romstage/northbridge/intel/sandybridge/raminit_sandy.o
CC romstage/northbridge/intel/sandybridge/romstage.o
CC romstage/southbridge/intel/bd82x6x/early_me.o
CC romstage/southbridge/intel/bd82x6x/early_pch.o
CC romstage/southbridge/intel/bd82x6x/early_pch_common.o
CC romstage/southbridge/intel/bd82x6x/early_rcba.o
CC romstage/southbridge/intel/bd82x6x/early_smbus.o
CC romstage/southbridge/intel/bd82x6x/early_spi.o
CC romstage/southbridge/intel/bd82x6x/early_thermal.o
CC romstage/southbridge/intel/bd82x6x/early_usb.o
CC romstage/southbridge/intel/bd82x6x/me_status.o
CC romstage/southbridge/intel/common/gpio.o
CC romstage/southbridge/intel/common/pmbase.o
CC romstage/southbridge/intel/common/reset.o
CC romstage/southbridge/intel/common/rtc.o
CC romstage/southbridge/intel/common/smbus.o
CC romstage/southbridge/intel/common/spi.o
CC romstage/superio/nuvoton/common/early_serial.o
LINK cbfs/fallback/romstage.debug
OBJCOPY cbfs/fallback/romstage.elf
CC ramstage/superio/nuvoton/nct6776/superio.o
CC ramstage/superio/common/conf_mode.o
CC ramstage/southbridge/intel/common/acpi_pirq_gen.o
CC ramstage/southbridge/intel/common/gpio.o
CC ramstage/southbridge/intel/common/madt.o
CC ramstage/southbridge/intel/common/pciehp.o
CC ramstage/southbridge/intel/common/pmbase.o
CC ramstage/southbridge/intel/common/pmutil.o
CC ramstage/southbridge/intel/common/rcba_pirq.o
CC ramstage/southbridge/intel/common/reset.o
CC ramstage/southbridge/intel/common/rtc.o
CC ramstage/southbridge/intel/common/smbus.o
CC ramstage/southbridge/intel/common/smi.o
CC ramstage/southbridge/intel/common/spi.o
CC ramstage/southbridge/intel/bd82x6x/azalia.o
CC ramstage/southbridge/intel/bd82x6x/early_pch_common.o
CC ramstage/southbridge/intel/bd82x6x/lpc.o
CC ramstage/southbridge/intel/bd82x6x/me.o
CC ramstage/southbridge/intel/bd82x6x/me_8.x.o
CC ramstage/southbridge/intel/bd82x6x/me_status.o
CC ramstage/southbridge/intel/bd82x6x/pch.o
CC ramstage/southbridge/intel/bd82x6x/pci.o
CC ramstage/southbridge/intel/bd82x6x/pcie.o
CC ramstage/southbridge/intel/bd82x6x/sata.o
CC ramstage/southbridge/intel/bd82x6x/smbus.o
CC ramstage/southbridge/intel/bd82x6x/usb_ehci.o
CC ramstage/southbridge/intel/bd82x6x/usb_xhci.o
CC ramstage/southbridge/intel/bd82x6x/watchdog.o
CC ramstage/northbridge/intel/sandybridge/acpi.o
CC ramstage/northbridge/intel/sandybridge/common.o
CC ramstage/northbridge/intel/sandybridge/gma.o
CC ramstage/northbridge/intel/sandybridge/northbridge.o
CC ramstage/northbridge/intel/sandybridge/pcie.o
CC ramstage/northbridge/intel/sandybridge/ram_calc.o
CC ramstage/mainboard/asus/p8h61-m_pro/static.o
CC ramstage/mainboard/asus/p8h61-m_pro/acpi_tables.o
GENERATE libhwbase/common/hw-config.ads
GENERATE libgfxinit/common/hw-gfx-gma-config.ads
GCC ramstage/mainboard/asus/p8h61-m_pro/gma-mainboard.o
CC ramstage/mainboard/asus/p8h61-m_pro/hda_verb.o
GCC ramstage/libhwbase/debug/hw-debug.o
GCC ramstage/libhwbase/common/direct/hw-pci-dev.o
GCC ramstage/libhwbase/common/hw-mmio_regs.o
GCC ramstage/libhwbase/common/hw-pci-mmconf.o
GCC ramstage/libhwbase/common/hw-pci.o
GCC ramstage/libhwbase/common/hw-port_io.o
GCC ramstage/libhwbase/common/hw-sub_regs.o
GCC ramstage/libhwbase/common/hw-time.o
GCC ramstage/libhwbase/common/hw.o
GCC ramstage/libhwbase/common/hw-config.o
GCC ramstage/libhwbase/ada/dynamic_mmio/hw-mmio_range.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-connectors-edp.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-connectors-fdi.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-connectors.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-pch-dp.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-pch-hdmi.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-pch-lvds.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-plls.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-port_detect.o
GCC ramstage/libgfxinit/common/ironlake/hw-gfx-gma-power_and_clocks.o
GCC
ramstage/libgfxinit/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.o
GCC ramstage/libgfxinit/common/hw-gfx-dp_aux_ch.o
GCC ramstage/libgfxinit/common/hw-gfx-dp_defs.o
GCC ramstage/libgfxinit/common/hw-gfx-dp_info.o
GCC ramstage/libgfxinit/common/hw-gfx-dp_training.o
GCC ramstage/libgfxinit/common/hw-gfx-edid.o
GCC ramstage/libgfxinit/common/hw-gfx-framebuffer_filler.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-config_helpers.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-connector_info.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-display_probing.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-dp_aux_ch.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-dp_aux_request.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-dp_info.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-i2c.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-panel.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-pch-fdi.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-pch-sideband.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-pch-transcoder.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-pch-vga.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-pch.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-pipe_setup.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-registers.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-transcoder.o
GCC ramstage/libgfxinit/common/hw-gfx-gma.o
GCC ramstage/libgfxinit/common/hw-gfx-i2c.o
GCC ramstage/libgfxinit/common/hw-gfx.o
GCC ramstage/libgfxinit/common/hw-gfx-gma-config.o
CC ramstage/lib/b64_decode.o
CC ramstage/lib/boot_device.o
CC ramstage/lib/bootmem.o
CC ramstage/lib/bootmode.o
GCC ramstage/lib/cb.o
CC ramstage/lib/cbfs.o
CC ramstage/lib/cbmem_common.o
CC ramstage/lib/cbmem_console.o
CC ramstage/lib/compute_ip_checksum.o
CC ramstage/lib/coreboot_table.o
CC ramstage/lib/delay.o
CC ramstage/lib/dimm_info_util.o
CC ramstage/lib/edid.o
CC ramstage/lib/ext_stage_cache.o
CC ramstage/lib/fallback_boot.o
CC ramstage/lib/fmap.o
CC ramstage/lib/gcc.o
CC ramstage/lib/halt.o
CC ramstage/lib/hardwaremain.o
CC ramstage/lib/hexdump.o
CC ramstage/lib/hexstrtobin.o
GCC ramstage/lib/hw-time-timer.o
CC ramstage/lib/imd.o
CC ramstage/lib/imd_cbmem.o
CC ramstage/lib/list.o
CC ramstage/lib/lzma.o
CC ramstage/lib/lzmadecode.o
CC ramstage/lib/malloc.o
CC ramstage/lib/memchr.o
CC ramstage/lib/memcmp.o
CC ramstage/lib/memrange.o
CC ramstage/lib/prog_loaders.o
CC ramstage/lib/prog_ops.o
CC ramstage/lib/region_file.o
CC ramstage/lib/reset.o
CC ramstage/lib/rmodule.o
CC ramstage/lib/romstage_handoff.o
CC ramstage/lib/romstage_stack.o
CC ramstage/lib/rtc.o
CC ramstage/lib/selfboot.o
CC ramstage/lib/stack.o
CC ramstage/lib/string.o
CC ramstage/lib/timestamp.o
CC ramstage/lib/version.o
CC ramstage/lib/wrdd.o
CC ramstage/drivers/uart/uart8250io.o
CC ramstage/drivers/uart/util.o
CC ramstage/drivers/spi/adesto.o
CC ramstage/drivers/spi/amic.o
CC ramstage/drivers/spi/atmel.o
CC ramstage/drivers/spi/bitbang.o
CC ramstage/drivers/spi/boot_device_rw_nommap.o
CC ramstage/drivers/spi/eon.o
CC ramstage/drivers/spi/gigadevice.o
CC ramstage/drivers/spi/macronix.o
CC ramstage/drivers/spi/spansion.o
CC ramstage/drivers/spi/spi-generic.o
CC ramstage/drivers/spi/spi_flash.o
CC ramstage/drivers/spi/sst.o
CC ramstage/drivers/spi/stmicro.o
CC ramstage/drivers/spi/winbond.o
CC ramstage/drivers/pc80/rtc/mc146818rtc.o
CC ramstage/drivers/pc80/pc/i8254.o
CC ramstage/drivers/pc80/pc/i8259.o
CC ramstage/drivers/pc80/pc/isa-dma.o
CC ramstage/drivers/pc80/pc/keyboard.o
CC ramstage/drivers/mrc_cache/mrc_cache.o
CC ramstage/drivers/intel/wifi/wifi.o
GCC ramstage/drivers/intel/gma/hires_fb/gma.o
CC ramstage/drivers/intel/gma/acpi.o
CC ramstage/drivers/intel/gma/opregion.o
CC ramstage/drivers/asmedia/aspm_blacklist.o
CC ramstage/device/cardbus_device.o
CC ramstage/device/cpu_device.o
CC ramstage/device/device.o
CC ramstage/device/device_const.o
CC ramstage/device/device_util.o
CC ramstage/device/i2c.o
CC ramstage/device/i2c_bus.o
CC ramstage/device/pci_class.o
CC ramstage/device/pci_device.o
CC ramstage/device/pci_ops.o
CC ramstage/device/pci_rom.o
CC ramstage/device/pciexp_device.o
CC ramstage/device/pcix_device.o
CC ramstage/device/pnp_device.o
CC ramstage/device/root_device.o
CC ramstage/device/smbus_ops.o
CC ramstage/cpu/x86/tsc/delay_tsc.o
CC smm/mainboard/asus/p8h61-m_pro/static.o
CC smm/arch/x86/memcpy.o
CC smm/arch/x86/memmove.o
CC smm/arch/x86/memset.o
CC smm/arch/x86/mmap_boot.o
CC smm/commonlib/cbfs.o
CC smm/commonlib/iobuf.o
CC smm/commonlib/region.o
CC smm/console/die.o
CC smm/cpu/intel/common/fsb.o
CC smm/cpu/intel/model_206ax/common.o
CC smm/cpu/intel/model_206ax/finalize.o
CC smm/cpu/intel/model_206ax/tsc_freq.o
CC smm/cpu/x86/pae/pgtbl.o
CC smm/cpu/x86/smm/smm_module_handler.o
CC smm/cpu/x86/tsc/delay_tsc.o
CC smm/device/device_const.o
CC smm/drivers/pc80/rtc/mc146818rtc.o
CC smm/lib/boot_device.o
CC smm/lib/cbfs.o
CC smm/lib/delay.o
CC smm/lib/fmap.o
CC smm/lib/gcc.o
CC smm/lib/halt.o
CC smm/lib/hexdump.o
CC smm/lib/malloc.o
CC smm/lib/memcmp.o
CC smm/lib/reset.o
CC smm/lib/version.o
CC smm/northbridge/intel/sandybridge/common.o
CC smm/northbridge/intel/sandybridge/finalize.o
CC smm/southbridge/intel/bd82x6x/me.o
CC smm/southbridge/intel/bd82x6x/me_8.x.o
CC smm/southbridge/intel/bd82x6x/pch.o
CC smm/southbridge/intel/bd82x6x/smihandler.o
CC smm/southbridge/intel/common/finalize.o
CC smm/southbridge/intel/common/gpio.o
CC smm/southbridge/intel/common/pmbase.o
CC smm/southbridge/intel/common/pmutil.o
CC smm/southbridge/intel/common/rtc.o
CC smm/southbridge/intel/common/smihandler.o
CP rmodules_x86_32/lib/rmodule.ld
OBJCOPY ramstage/cpu/x86/smm/smm.manual
CC smmstub/cpu/x86/smm/smm_stub.o
OBJCOPY ramstage/cpu/x86/smm/smmstub.manual
CC ramstage/cpu/x86/smm/smm_module_loader.o
CC ramstage/cpu/x86/pae/pgtbl.o
CC ramstage/cpu/x86/name/name.o
CC ramstage/cpu/x86/mtrr/debug.o
CC ramstage/cpu/x86/mtrr/mtrr.o
CC ramstage/cpu/x86/lapic/boot_cpu.o
CC ramstage/cpu/x86/lapic/lapic.o
CC ramstage/cpu/x86/lapic/lapic_cpu_init.o
CC ramstage/cpu/x86/lapic/secondary.o
CC ramstage/cpu/x86/cache/cache.o
CC rmodules_x86_32/cpu/x86/sipi_vector.o
OBJCOPY ramstage/cpu/x86/sipi_vector.manual
CC ramstage/cpu/x86/backup_default_smm.o
CC ramstage/cpu/x86/mp_init.o
CC ramstage/cpu/intel/turbo/turbo.o
CC ramstage/cpu/intel/smm/gen1/smmrelocate.o
CC ramstage/cpu/intel/model_206ax/acpi.o
CC ramstage/cpu/intel/model_206ax/common.o
CC ramstage/cpu/intel/model_206ax/model_206ax_init.o
CC ramstage/cpu/intel/model_206ax/stage_cache.o
CC ramstage/cpu/intel/model_206ax/tsc_freq.o
CC ramstage/cpu/intel/microcode/microcode.o
CC ramstage/cpu/intel/common/common_init.o
CC ramstage/console/console.o
CC ramstage/console/die.o
GCC ramstage/console/hw-debug_sink.o
CC ramstage/console/init.o
CC ramstage/console/post.o
CC ramstage/console/printk.o
CC ramstage/console/vsprintf.o
CC ramstage/console/vtxprintf.o
CC ramstage/commonlib/cbfs.o
CC ramstage/commonlib/iobuf.o
CC ramstage/commonlib/lz4_wrapper.o
CC ramstage/commonlib/mem_pool.o
CC ramstage/commonlib/region.o
CC ramstage/commonlib/sort.o
CC ramstage/arch/x86/acpi.o
CC ramstage/arch/x86/acpi_device.o
CC ramstage/arch/x86/acpi_pld.o
CC ramstage/arch/x86/acpi_s3.o
CC ramstage/arch/x86/acpigen.o
CC ramstage/arch/x86/acpigen_dsm.o
CC ramstage/arch/x86/boot.o
CC ramstage/arch/x86/c_start.o
CC ramstage/arch/x86/cbmem.o
CC ramstage/arch/x86/cf9_reset.o
CC ramstage/arch/x86/cpu.o
CC ramstage/arch/x86/cpu_common.o
CC ramstage/arch/x86/ebda.o
CC ramstage/arch/x86/exception.o
CC ramstage/arch/x86/gdt.o
CC ramstage/arch/x86/idt.o
CC ramstage/arch/x86/ioapic.o
CC ramstage/arch/x86/memcpy.o
CC ramstage/arch/x86/memmove.o
CC ramstage/arch/x86/memset.o
CC ramstage/arch/x86/mmap_boot.o
CC ramstage/arch/x86/rdrand.o
CC ramstage/arch/x86/smbios.o
CC ramstage/arch/x86/tables.o
CC ramstage/arch/x86/timestamp.o
CC ramstage/arch/x86/wakeup.o
CC ramstage/acpi/sata.o
GCC ramstage/cb-config.o
CP ramstage/arch/x86/memlayout.ld
CP ramstage/lib/program.ld
BIND ramstage/b__ramstage.adb
GCC ramstage/b__ramstage.o
CC generated/ramstage.o
CC cbfs/fallback/ramstage.debug
CREATE build/mainboard/asus/p8h61-m_pro/cbfs-file.Oh3wfp.out (from
/home/xxx/bios/coreboot/.config)
CC postcar/mainboard/asus/p8h61-m_pro/static.o
CC postcar/arch/x86/acpi_s3.o
CC postcar/arch/x86/boot.o
CC postcar/arch/x86/cbfs_and_run.o
CC postcar/arch/x86/cbmem.o
CC postcar/arch/x86/cf9_reset.o
CC postcar/arch/x86/cpu_common.o
CC postcar/arch/x86/exit_car.o
CC postcar/arch/x86/gdt_init.o
CC postcar/arch/x86/memcpy.o
CP postcar/arch/x86/memlayout.ld
CC postcar/arch/x86/memmove.o
CC postcar/arch/x86/memset.o
CC postcar/arch/x86/mmap_boot.o
CC postcar/arch/x86/postcar.o
CC postcar/arch/x86/timestamp.o
CC postcar/commonlib/cbfs.o
CC postcar/commonlib/iobuf.o
CC postcar/commonlib/lz4_wrapper.o
CC postcar/commonlib/mem_pool.o
CC postcar/commonlib/region.o
CC postcar/console/console.o
CC postcar/console/die.o
CC postcar/console/init.o
CC postcar/console/post.o
CC postcar/console/printk.o
CC postcar/console/vsprintf.o
CC postcar/console/vtxprintf.o
CC postcar/cpu/intel/car/non-evict/exit_car.o
CC postcar/cpu/intel/model_206ax/stage_cache.o
CC postcar/cpu/intel/model_206ax/tsc_freq.o
CC postcar/cpu/x86/lapic/boot_cpu.o
CC postcar/cpu/x86/mtrr/debug.o
CC postcar/cpu/x86/pae/pgtbl.o
CC postcar/cpu/x86/tsc/delay_tsc.o
CC postcar/device/device_const.o
CC postcar/device/pci_early.o
CC postcar/drivers/pc80/rtc/mc146818rtc.o
CC postcar/drivers/spi/adesto.o
CC postcar/drivers/spi/amic.o
CC postcar/drivers/spi/atmel.o
CC postcar/drivers/spi/bitbang.o
CC postcar/drivers/spi/eon.o
CC postcar/drivers/spi/gigadevice.o
CC postcar/drivers/spi/macronix.o
CC postcar/drivers/spi/spansion.o
CC postcar/drivers/spi/spi-generic.o
CC postcar/drivers/spi/spi_flash.o
CC postcar/drivers/spi/sst.o
CC postcar/drivers/spi/stmicro.o
CC postcar/drivers/spi/winbond.o
CC postcar/drivers/uart/uart8250io.o
CC postcar/drivers/uart/util.o
CC postcar/lib/boot_device.o
CC postcar/lib/bootmode.o
CC postcar/lib/cbfs.o
CC postcar/lib/cbmem_common.o
CC postcar/lib/cbmem_console.o
CC postcar/lib/delay.o
CC postcar/lib/ext_stage_cache.o
CC postcar/lib/fmap.o
CC postcar/lib/gcc.o
CC postcar/lib/halt.o
CC postcar/lib/imd.o
CC postcar/lib/imd_cbmem.o
CC postcar/lib/libgcc.o
CC postcar/lib/lzma.o
CC postcar/lib/lzmadecode.o
CC postcar/lib/memchr.o
CC postcar/lib/memcmp.o
CC postcar/lib/prog_loaders.o
CC postcar/lib/prog_ops.o
CP postcar/lib/program.ld
CC postcar/lib/reset.o
CC postcar/lib/rmodule.o
CC postcar/lib/romstage_handoff.o
CC postcar/lib/timestamp.o
CC postcar/lib/version.o
CC postcar/northbridge/intel/sandybridge/ram_calc.o
CC postcar/southbridge/intel/common/pmbase.o
CC postcar/southbridge/intel/common/reset.o
CC postcar/southbridge/intel/common/rtc.o
CC postcar/southbridge/intel/common/spi.o
LINK cbfs/fallback/postcar.debug
IASL build/dsdt.aml
Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20190108
Copyright (c) 2000 - 2019 Intel Corporation
coreboot toolchain vc3c9afbdf1 2019-02-03
dsdt.asl 84: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 98: Offset (0x11),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 135: Offset (0x3c),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 143: Offset (0x46),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 357: Offset (0x81),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 362: Offset (0x82),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 367: Offset (0x83),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 372: Offset (0x84),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 377: Offset (0x85),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 382: Offset (0x86),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 913: Offset(0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 918: Offset(0x04),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 966: Offset(0x30),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 971: Offset(0x34),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 976: Offset(0x38),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 1032: Offset(0x0000),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
ASL Input: dsdt.asl - 1992 lines, 34668 bytes, 823 keywords
AML Output: dsdt.aml - 9735 bytes, 374 named objects, 449 executable opcodes
Compilation complete. 0 Errors, 0 Warnings, 16 Remarks, 227 Optimizations, 1
Constants Folded
IASL build/dsdt.aml disassembled correctly.
Created CBFS (capacity = 982488 bytes)
CBFS fallback/romstage
CBFS cpu_microcode_blob.bin
CBFS fallback/ramstage
CBFS config
CBFS revision
CBFS cmos_layout.bin
CBFS fallback/postcar
CBFS fallback/dsdt.aml
CBFS fallback/payload
DD Adding Intel Firmware Descriptor
IFDTOOL me.bin -> coreboot.pre
File build/coreboot.pre is 4194304 bytes
File bin/me.bin is 1568768 bytes
Adding bin/me.bin as the Intel ME section of build/coreboot.pre
Writing new image to build/coreboot.pre.new
IFDTOOL Unlocking Management Engine
File build/coreboot.pre is 4194304 bytes
Writing new image to build/coreboot.pre.new
CBFS coreboot.rom
CBFSLAYOUT coreboot.rom
This image contains the following sections that can be manipulated with this
tool:
'RW_MRC_CACHE' (size 65536, offset 3145728)
'COREBOOT' (CBFS, size 982528, offset 3211776)
It is possible to perform either the write action or the CBFS add/remove
actions on every section listed above.
To see the image's read-only sections as well, rerun with the -w option.
CBFSPRINT coreboot.rom
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 80644 none
cpu_microcode_blob.bin 0x13c00 microcode 25600 none
fallback/ramstage 0x1a080 stage 100982 none
config 0x32b40 raw 363 none
revision 0x32d00 raw 679 none
cmos_layout.bin 0x33000 cmos_layout 968 none
fallback/postcar 0x33400 stage 15732 none
fallback/dsdt.aml 0x371c0 raw 9735 none
fallback/payload 0x39840 simple elf 50614 none
(empty) 0x45e40 null 694168 none
bootblock 0xef600 bootblock 1984 none
Built asus/p8h61-m_pro (P8H61-M PRO)
$
$ sudo flashrom --programmer ch341a_spi -w build/coreboot.rom
flashrom v0.9.9-r1954 on Linux 4.9.0-8-amd64 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Calibrating delay loop... OK.
Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on ch341a_spi.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
$
$ cat defconfig
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_P8H61_M_PRO=y
CONFIG_IFD_BIN_PATH="bin/desc.bin"
CONFIG_ME_BIN_PATH="bin/me.bin"
CONFIG_HAVE_IFD_BIN=y
CONFIG_HAVE_ME_BIN=y
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_PAYLOAD_ELF=y
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
$
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