On Thu, Mar 28, 2019 at 06:55:50AM +0800, Rafael Send wrote: > Hi, > If I theoretically had a flash chip that was larger than 128Mb, it requires > 3-4 byte addressing. > > Does / could coreboot support such large memory, or would the limitation > live somewhere else in the system?
My guess is it depends first on the platform: If the integrated flash controller is not just plain SPI it has to support the 4 byte mode. Second on the coreboot driver: I've not checked if anything is implemented yet but I don't see limitations on the software side. Hope this helps, Julien VdG > > Cheers, > R > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
