[coreboot] Re: FSP 1.0: How to configure soldered memory with spd

[Ranga Rao]

Hi Alexey,

For memory down configuration ensure below are enabled/filled in FSP

When a DIMM is having its SPD, the smbus reads the SPD and configures the DIMM 
channels

For Memory down below changes are expected


  1.  UpdData->MemoryDownEnable is enabled

        2)
  MEMORY_DOWN_DATA            PcdMemoryParameters;           /* Offset 0x00F0 */
  UINT16                      PcdRegionTerminator;           /* Offset 0x0100 */
} UPD_DATA_REGION

You can check this function below

romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
                UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;

                /* Memory Down overriding */
                UpdData->PcdMemoryParameters.EnableMemoryDown = 1;
                UpdData->PcdMemoryParameters.DRAMSpeed = 1;      /* DRAM Speed  
*/
                UpdData->PcdMemoryParameters.DRAMType = 1;       /* DRAM Type */
                UpdData->PcdMemoryParameters.DIMM0Enable = 1;    /* DIMM 0 
Enable */
                UpdData->PcdMemoryParameters.DIMM1Enable = 0;    /* DIMM 1 
Enable */
                UpdData->PcdMemoryParameters.DIMMDWidth = 1;     /* DRAM device 
data width */
#if           CONFIG_MINNOWMAX_2GB_SKU
                UpdData->PcdMemoryParameters.DIMMDensity = 2;    /* DRAM device 
data density 2GB */
#else
                UpdData->PcdMemoryParameters.DIMMDensity = 1;    /* DRAM device 
data density 1GB */
#endif
                UpdData->PcdMemoryParameters.DIMMDensity = 2;    /* DRAM device 
data density */
                UpdData->PcdMemoryParameters.DIMMBusWidth = 3;   /* DIMM Bus 
Width */
                UpdData->PcdMemoryParameters.DIMMSides = 0;      /* Ranks Per 
DIMM */
                UpdData->PcdMemoryParameters.DIMMtCL = 7;        /* tCL */
                UpdData->PcdMemoryParameters.DIMMtRPtRCD = 7;    /* tRP and 
tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
                UpdData->PcdMemoryParameters.DIMMtWR = 8;        /* tWR in DRAM 
clk  */
                UpdData->PcdMemoryParameters.DIMMtWTR = 4;       /* tWTR in 
DRAM clk */
                UpdData->PcdMemoryParameters.DIMMtRRD = 6;       /* tRRD in 
DRAM clk */
                UpdData->PcdMemoryParameters.DIMMtRTP = 4;       /* tRTP in 
DRAM clk */
                UpdData->PcdMemoryParameters.DIMMtFAW = 14;      /* tFAW in 
DRAM clk */

Regards
Ranga


From: Alexey Borovikov <realman....@gmail.com>
Sent: 02 May 2019 09:20
To: coreboot@coreboot.org
Subject: [coreboot] FSP 1.0: How to configure soldered memory with spd

There are two boards Intel Atom E3825 with soldered memory. One board with spd, 
the other without spd. For a board where there is no spd, after configure the 
correct memory settings in the fsp, I get a working memory controller. For a 
board with spd, the fsp configurator does not allow to select soldered memory 
with spd.

How to configure the board with soldered memory where spd?
Is there any difference when using a memory controller with soldered memory 
with spd and DIMM?
FSP 1.0 is working with a chip spd on a smbus?

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