On Mon, Jun 10, 2019 at 9:15 PM Andrew A. I. <[email protected]> wrote: > > Hello! > Please, someone tell me, why SeaBIOS changing e820 memory map for 0x100000 - > 0x7ff2dfff region? For example: >
Could you collect and share the coreboot logs with 'util/cbmem -1'. I've seen similar hibernate/resume failure before, it was then related to the changed memory layout of coreboot tables (which is reflected in the e820 table SeaBIOS creates). In short, hibernate (ACPI S4) does not work on the first boot after flashing firmware or change of DIMMs. It's about MRC CACHE being allocated in CBMEM for the initial boot, but not the following resume boots. If this is your case too, there should be an easy fix by adding a dummy reserve, but sounds like nobody has taken the initiative to submit such change. As an alternative solution, I would like to see runtime code to mask of ACPI S4 and S3 features from SSDT/DSDT. Kyösti _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
