On 01.07.19 14:53, Andriy Gapon wrote: Hi,
speaking w/ my linux apu2/3 platform driver maintainer hat on: > I am using a PCEngines APU2 system and I noticed that its HPET timers do not > advertise FSB (MSI) interrupt delivery capability. That is interesting. Can you give us something to reproduce the problem (test-cases, etc) ? Could you test whether it's just I was under the impression that the g412's x86 cores are pretty straightforward, but maybe I'm wrong. So another 2do on my list ... > That is despite the fact that BKDG for family 16h models 30h - 3Fh says that > those capability bits are hardwired to 1. > I took a quick look through coreboot sources (APU2 firmware is coreboot) and > noticed something interesting. It seems that the repository includes code for > AGESA (src/vendorcode/amd/agesa) and there I see that the MSI capability can > be > turned on / off via a special PM I/O register. It appears that HPET MSI > support > is disabled on some platforms by default: > > src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c: > TRUE, // HpetMsiDis > src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c: > TRUE, // HpetMsiDis > > Does anyone know what is a reason for that? Maybe the HPET core can be attached in different ways inside the SoC. The name "disable" sounds like the standard behaviour is enabled, but can be disabled if really needed. On my Box, Linux reports using IO-APIC. I think because cpuid has arat flag (always running apic timer). My wild guess is that HPET isn't used at all in this case. (perhaps because using it seems not very efficient) --mtx -- Enrico Weigelt, metux IT consult Free software and Linux embedded engineering [email protected] -- +49-151-27565287 _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
