On Fri, Jul 5, 2019 at 5:36 PM Mike Banon <mikeb...@gmail.com> wrote: > > Thank you for advice. I followed the instructions of this change, and > after fixing a few compilation errors (had to replace a few %x with > %llu at printf's) - using the same .config - I got a ROM which is > unbootable! Maybe because I don't have AMD HDT Debugger, and it > should've been connected to some usually-not-soldered header for this > ROM to boot?
You don't need HDT debugger. At least I have not experienced IDS troubles because of not having one connected. But go through the IDS options... > Perhaps I can manually redirect these IDS prints to a standard > coreboot log - if that will give some useful info. Or I could dive > into AGESA and replace all DDR1333 stuff with a DDR1866 one, to force > it running as 1866MHz CL9 - since that "#define > BLDCFG_MEMORY_CLOCK_SELECT" seemingly doesn't work for some reason. That's what is supposed to happen already, it should dump all IDS debug on serial console. Or whatever console you have enabled, IDS is routed to printk(). Boots will be slow due the amount of data, maybe 30 seconds or so to get past ram training. There's lots of filtering inside AGESA you can adjust. Kyösti _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
