Hello, If the board you have is not exactly the Intel Mohonpeak RVP, using the RVP code as-is on your board is bound to fail, and can even cause damage (shortcircuits on GPIO pins).
Regards, Angel Pons On Thu, Jul 11, 2019, 21:56 Martin Roth <[email protected]> wrote: > I'd check the smbus base address right before the FSP starts with and > without your change. If it's only set with your change, then try > clearing it before calling the FSP. > See what the BAR is after the FSP runs, and make sure that the address > coreboot is using is the same. The early FSPs had a bad habit of > dying if any register values weren't what they expected. > > Martin > > On Thu, Jul 11, 2019 at 1:10 PM <[email protected]> wrote: > > > > Motherboard based on the Intel Rangeley Atom C2000 (C2758) processor. On > the board installed Nuvoton NCT6776F/D superIO. > > For its correct operation, a frequency of 48 MHz is necessary, which > must be enabled by write some bits in IDT clock synthesizer (9VRS4420DKLFT). > > The configuration of the synthesizer is made thrue SMBus0, synthesizer > address is 0x69. > > > > As the base, I used the source code of the reference Intel motherboard > MohonPeak. > > Initialization should be done as early as possible - preferable before > FSP initializing. > > At main() function in > coreboot/src/southbridge/intel/fsp_rangeley/romstage.c. > > For example after early_mainboard_romstage_entry() function call and > before fsp_early_init function call). > > > > The problem is that after just reading byte on the SMBus0 initialization > of FSP fails. I specifically conducted the experiments - I did not load the > synthesizer, but simply read through SMBus0. > > Coerboot hangs with post code 0x92 (Going to call into FSP binary for > MemoryInit phase #define POST_FSP_MEMORY_INIT 0x92). > > If I move my code after FSP initialization, the system was booting > normal. > > > > How can the reading by SMBus0 affect the FSP initialization process > (FSP_MEMORY_INIT)? > > During the FSP_MEMORY_INIT process, FSP must read data from the memory > modules SPD eeprom (thrue SMBus/i2c 0x50, 0x52). > > Maybe this is the problem? Is it possible to return SMBus0 controller > to its initial state after using? > > > > Full source: https://review.coreboot.org/c/coreboot/+/34193/4 > > > > Booting log: > > > > coreboot-4.9-2383-g9e1bf2e2d2 Thu Jul 11 14:29:28 UTC 2019 romstage > starting (log level: 8)... > > Setting up static southbridge registers... done. > > Disabling Watchdog timer... done. > > RTC Init > > Starting the Intel FSP (early_init) > > CBFS @ 600200 size 1ffe00 > > CBFS: 'Master Header Locator' located CBFS at [600200:800000) > > CBFS: Locating 'cpu_microcode_blob.bin' > > CBFS: Checking offset 0 > > CBFS: File @ offset 0 size 20 > > CBFS: Unmatched 'cbfs master header' at 0 > > CBFS: Checking offset 80 > > CBFS: File @ offset 80 size 7244 > > CBFS: Unmatched 'fallback/romstage' at 80 > > CBFS: Checking offset 7340 > > CBFS: File @ offset 7340 size 2ab > > CBFS: Unmatched 'config' at 7340 > > CBFS: Checking offset 7640 > > CBFS: File @ offset 7640 size 2a1 > > CBFS: Unmatched 'revision' at 7640 > > CBFS: Checking offset 7940 > > CBFS: File @ offset 7940 size 444 > > CBFS: Unmatched 'cmos_layout.bin' at 7940 > > CBFS: Checking offset 7dc0 > > CBFS: File @ offset 7dc0 size 2af0 > > CBFS: Unmatched 'fallback/dsdt.aml' at 7dc0 > > CBFS: Checking offset a900 > > CBFS: File @ offset a900 size 642 > > CBFS: Unmatched 'payload_config' at a900 > > CBFS: Checking offset af80 > > CBFS: File @ offset af80 size e8 > > CBFS: Unmatched 'payload_revision' at af80 > > CBFS: Checking offset b0c0 > > CBFS: File @ offset b0c0 size 8 > > CBFS: Unmatched 'etc/sercon-port' at b0c0 > > CBFS: Checking offset b100 > > CBFS: File @ offset b100 size 4c98 > > CBFS: Unmatched '' at b100 > > CBFS: Checking offset fdc0 > > CBFS: File @ offset fdc0 size 10000 > > CBFS: Unmatched 'mrc.cache' at fdc0 > > CBFS: Checking offset 1fe00 > > CBFS: File @ offset 1fe00 size 14c00 > > CBFS: Found @ offset 1fe00 size 14c00 > > microcode: sig=0x406d8 pf=0x1 revision=0x12a > > microcode: Update skipped, already up-to-date > > Configure Default UPD Data > > PcdEnableIQAT 1 > > PcdEnableLan 1 > > PcdEnableLan 1 > > PcdEnableLan 1 > > PcdEnableLan 1 > > PcdEnableUsb20 1 > > PcdEnableSata2 1 > > PcdEnableSata3 1 > > PcdPcieRootPort1DeEmphasis:0x00 (default) > > PcdPcieRootPort2DeEmphasis:0x00 (default) > > PcdPcieRootPort3DeEmphasis:0x00 (default) > > PcdPcieRootPort4DeEmphasis:0x00 (default) > > CBFS @ 600200 size 1ffe00 > > CBFS: 'Master Header Locator' located CBFS at [600200:800000) > > CBFS: Locating 'mrc.cache' > > CBFS: Checking offset 0 > > CBFS: File @ offset 0 size 20 > > CBFS: Unmatched 'cbfs master header' at 0 > > CBFS: Checking offset 80 > > CBFS: File @ offset 80 size 7244 > > CBFS: Unmatched 'fallback/romstage' at 80 > > CBFS: Checking offset 7340 > > CBFS: File @ offset 7340 size 2ab > > CBFS: Unmatched 'config' at 7340 > > CBFS: Checking offset 7640 > > CBFS: File @ offset 7640 size 2a1 > > CBFS: Unmatched 'revision' at 7640 > > CBFS: Checking offset 7940 > > CBFS: File @ offset 7940 size 444 > > CBFS: Unmatched 'cmos_layout.bin' at 7940 > > CBFS: Checking offset 7dc0 > > CBFS: File @ offset 7dc0 size 2af0 > > CBFS: Unmatched 'fallback/dsdt.aml' at 7dc0 > > CBFS: Checking offset a900 > > CBFS: File @ offset a900 size 642 > > CBFS: Unmatched 'payload_config' at a900 > > CBFS: Checking offset af80 > > CBFS: File @ offset af80 size e8 > > CBFS: Unmatched 'payload_revision' at af80 > > CBFS: Checking offset b0c0 > > CBFS: File @ offset b0c0 size 8 > > CBFS: Unmatched 'etc/sercon-port' at b0c0 > > CBFS: Checking offset b100 > > CBFS: File @ offset b100 size 4c98 > > CBFS: Unmatched '' at b100 > > CBFS: Checking offset fdc0 > > CBFS: File @ offset fdc0 size 10000 > > CBFS: Found @ offset fdc0 size 10000 > > find_current_mrc_cache_local: No valid fast boot cache found. > > FSP MRC cache not present. > > _______________________________________________ > > coreboot mailing list -- [email protected] > > To unsubscribe send an email to [email protected] > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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