For some reason, the console log that I attempted to attach did not seem to
reach the list. I'll paste it here:
"coreboot-4.10-528-g809b7513a2-2.0-beta1 Mon Sep 2 20:08:20 UTC 2019 bootblock
starting (log level: 7)...
CPU: Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz
CPU: ID 406e3, Skylake D0, ucode: 000000cb
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 1904 (rev 08) is Skylake-U
PCH: device id 9d48 (rev 21) is Skylake-U Premium
IGD: device id 1916 (rev 07) is Skylake ULT GT2
misccfg_mask:fff000ff misccfg_value:43200
CBFS: 'Master Header Locator' located CBFS at [270200:800000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size b3cc" (many null characters follow, but this is
the end of the log)
I looked into FSP-T (TempRamInit on FSP 2.0) and apparently it does not support
Skylake. That shouldn't be a problem, I've seen some laptops supported by
coreboot using its 'common' cache-as-RAM, but it made me more certain that it's
my romstage code at fault (FSP-T isn't needed, coreboot works on these laptops,
etc).
I ended up investigating romstage.c + pei_data.c vs only romstage.c to discover
that the former was deprecated and that ultimately, the code that I had been
using for romstage.c with FSP 2.0 may have been a leftover from when I had been
trying to use FSP 1.1. I'll paste a diff below in case it helps/anyone is
interested.
"--- thenromstage.c 2019-09-18 15:18:13.165824532 +1000
+++ romstage.c 2019-09-17 19:26:56.417327000 +1000
@@ -16,12 +16,12 @@
* GNU General Public License for more details.
*/
-#include <string.h>
#include <assert.h>
#include <soc/romstage.h>
#include <spd_bin.h>
+#include <string.h>
-static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
+static void mainboard_fill_dq_map_data(void *dq_map_ptr)
{
/* DQ byte map */
const u8 dq_map[2][12] = {
@@ -29,18 +29,16 @@
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
- memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
- memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}
-static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
+static void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
{ 0, 1, 3, 2, 4, 5, 6, 7 },
{ 1, 0, 4, 5, 2, 3, 6, 7 } };
- memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
- memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
}
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
@@ -70,10 +68,8 @@
dump_spd_info(&blk);
assert(blk.spd_array[0][0] != 0);
- mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
- &mem_cfg->DqByteMapCh1);
- mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
- &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
"
While I unfortunately can't test anything for the moment because my Pi is out
of commission, I'll reconfigure the devicetree based on values extracted from
the OEM's BIOS and hope that this gets me a somewhat working port.
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