Hi,
Search your devicetree.cb for UART PCI devices like:
device pci 19.2 on end # UART #2
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
As you can see above these entries describe the device.function of the
UART and the on/off switch. Try to turn them on and see what happens.
Additionally you will have to have an array defining SerialIO devices in
devicetree like:
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
So it will pass the correct parameters to FSP. You have to either choose
PchSerialIoPci or PchSerialIoAcpi, depending on your needs.
Regards,
Michał
On 04.10.2019 16:19, Senthil Kumar G via coreboot wrote:
> Hi,
>
> I have added the wrong VBT file. Corrected it and display is coming.
>
> Is there any way to configure all uart of the processor. I am getting
> only one serial controller in list of lspci. Coffeelake has three uart
> ports but only one is getting listed.
>
> Thanks for the support.
>
> rgds,
> gsen
>
> On Friday, 4 October, 2019, 12:18:49 pm IST, Senthil Kumar G via
> coreboot <[email protected]> wrote:
>
>
> Hi,
>
> I have added the VBT in the coreboot.
>
> CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/intel/cflrvp/VbtCfl_h.bin"
>
> On Friday, 4 October, 2019, 11:26:19 am IST, Matt DeVillier
> <[email protected]> wrote:
>
>
> FSP can't initialize the graphics device without a valid VBT being
> loaded. Are you supplying that and setting the associated options in
> your config?
>
> On Fri, Oct 4, 2019, 12:32 AM Senthil Kumar G via coreboot
> <[email protected] <mailto:[email protected]>> wrote:
>
> Hi,
>
> We are developing coreboot along with UEFI shell payload for
> Coffelake architecture. We are using the processor integrated
> graphics controller for display.
>
> I am getting the following error on porting the coreboot.
>
> Grahics hand-off block not found.
> FSP did not return a valid framebuffer.
>
> I checked internal graphics is enabled in FSP and graphics memory
> is set to 32 MB. Also applied a patch found in coreboot mailing
> list on device tree and gpio files for Intel graphics.
>
> Whether Coreboot can print any messages on the display (other than
> console).
>
> Coreboot came up and I got the shell prompt on Uart Console. The
> same shell prompt has to come on the display (monitor) but not
> displayed. I suspect some graphics initialization problem.
>
> Regards,
> gsen.
>
>
>
>
>
>
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--
Michał Żygowski
Firmware Engineer
http://3mdeb.com | @3mdeb_com
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