Dear microcode experts, please give us some feedback on how to do microcode updates properly in coreboot.
While fixing a crash initializing Intel SGX on HT enabled CPUs I noticed that coreboot doesn't care for HT at all when doing MSR initialisation. I proposed the following patch [1], but it turns out that there are different opinions about updating microcode in parallel. In total there are four ways and only one can be correct: 1. Up to now coreboot updated all threads in parallel without a lock. That seems to follow Intel SDM (Order Number: 253668-070US) Chapter 8.7.11 2. According to Intel SDM (Order Number: 253668-070US) Chapter 9.11.6.3 microcode updates must only be done on one thread for each core, as long as the sibling thread doesn't do an update at time. 3. The kernel patch [2] states that the sibling thread must be idle while updating microcode on one core. 4. The "Bios Writers Guide" (Document Number 504790 / 550049) states that microcode must be done on all threads, but synchronized between sibling threads to only update one at a time. Which one is the correct way and how do you know? @Intel Can you update the SDM to clarify? Thank you for your time. 1: https://review.coreboot.org/c/coreboot/+/35739/ 2: https://lore.kernel.org/patchwork/patch/889353/ Regards, Patrick Rudolph 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: [email protected] Phone: +49 234 / 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 13207 Geschäftsführung: Eray Basar, Sebastian Deutsch _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
