Hi all, thanks for your answers! >Do you have working coreboot serial console and postcodes already? >Recent AMD SoCs have LPC clocks disabled and/or LPC pins as >multi-purpose. See hudson_lpc_port80() implementation and try adapt >from that to route IO 0x80 to LPC.
Yes, the serial console is working and I can see the post codes in the console. But I lost the trace once the code calls 'amd_init_post()' in the agesawrapper.c. I've read that the code sends POST codes and I was wondering if any is sent from that code. My board uses the stoneyridge AMD SOC and I've found that 'lpc_enable_port80()' is called by default on 'bootblock_fch_early_init()' from southbridge.c... I'll try to get something from the LPC. Thanks again! Jorge _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
