Hi Naveen, If you had the built-in serial enablement option off, it was the FSP which enabled the port instead of coreboot. Since FSP is called in the middle of romstage, the logs started from after-FSP part of romstage.
When built coreboot with the built-in serial port enablement, the serial port gets initialized by coreboot before FSP and befor econsole is initialized. The string: coreboot-4.10-984-gdd4c625469-dirty Mon Oct 14 18:32:09 UTC 2019 romstage starting (log level: 7) is actually printed by console_init(); function which is called before FSP and after built-in serial port is enabled. Hopefully this explanation is sufficient. Best regards, -- Michał Żygowski Firmware Engineer http://3mdeb.com | @3mdeb_com On 20.10.2019 14:22, Naveen Chaudhary wrote: > "Enable built-in legacy serial port" > > After I turn this on, I get the logs since the romstage beginning > (including fsp_init and next). > > But still I am not clear much, requesting some help to explain the > scenario. > > > Regards > Naveen > PS : with a dream to become an expert BIOS engineer > ------------------------------------------------------------------------ > *From:* Naveen Chaudhary <naveenchaudhary2...@hotmail.com> > *Sent:* Sunday, October 20, 2019 5:16 PM > *To:* coreboot@coreboot.org <coreboot@coreboot.org> > *Subject:* Re: Bootblock and Romstage logs getting skipped on first > boot and boot continues from ramstage instead > > From past 5 days, I have built and flashed coreboot a 100 times and I > could see the following line in every cold boot : > coreboot-4.10-984-gdd4c625469-dirty Mon Oct 14 18:32:09 UTC 2019 > romstage starting (log level: 7)... > > Now I never see this line, but instead its always the ramstage (no > romstage) as mentioned earlier. I have no code changes, except few > comments as a note to myself. In both the scenarios, I boot till the > bootloader successfully. > > I am surprised why I am not getting romstage logs?? I am physically > removing the power cable for cold boot, but still no romstage logs. > The romstage logs come only when the SeaBIOS waits for 60 seconds and > does a hard reboot. Physically removing the power cable directly leads > me to the ramstage. > > Regards, > Naveen > ------------------------------------------------------------------------ > *From:* Naveen Chaudhary > *Sent:* Sunday, October 20, 2019 4:48 PM > *To:* coreboot@coreboot.org <coreboot@coreboot.org> > *Subject:* Bootblock and Romstage logs getting skipped on first boot > and boot continues from ramstage instead > > Hi, > > The title seems pretty stupid but that's what I am observing on my > MinnowMax. When I have built coreboot and flashed and the moment I > connect the power cable back, I see the following logs (no romstage > beginning logs, no console_init logs): > > romstage_main_continue status: 0 hob_list_ptr: 7ae20000 > FSP Status: 0x0 > PM1_STS = 0x2000 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808 > romstage_main_continue: prev_sleep_state = S0 > Baytrail Chip Variant: Bay Trail-I (ISG/embedded) > MRC v0.102 > 1 channels of DDR3 @ 1066MHz > CBMEM: > IMD: root @ 7adff000 254 entries. > IMD: root @ 7adfec00 62 entries. > FMAP: Found "FLASH" version 1.1 at 500000. > FMAP: base = ff800000 size = 800000 #areas = 3 > SMM Memory Map > SMRAM : 0x7b000000 0x800000 > Subregion 0: 0x7b000000 0x700000 > Subregion 1: 0x7b700000 0x100000 > Subregion 2: 0x7b800000 0x0 > CBFS: 'Master Header Locator' located CBFS at [500200:800000) > CBFS: Locating 'fallback/ramstage' > CBFS: Found @ offset 2ca80 size ef16 > > > coreboot-4.10-984-gdd4c625469-dirty Mon Oct 14 18:32:09 UTC 2019 > ramstage starting (log level: 7)... > Moving GDT to 7adfe900...ok > BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 > CBFS: 'Master Header Locator' located CBFS at [500200:800000) > CBFS: Locating 'cpu_microcode_blob.bin' > CBFS: Found @ offset 1fe00 size cc00 > microcode: sig=0x30679 pf=0x1 revision=0x90c > CPUID: 00030679 > Cores: 2 > > However, when there is a hard reset by the SeaBIOS when there is no > bootable device found, I get the complete logs since the romstage. > > No bootable device. Retrying in 60 seconds. > Rebooting. > In resume (status=0) > In 32bit resume > Attempting a hard reboot > ACPI hard reset 1:cf9 (6) > > > coreboot-4.10-984-gdd4c625469-dirty Mon Oct 14 18:32:09 UTC 2019 > romstage starting (log level: 7)... *<--- This logs does not appear > in the first case.* > > Can someone please help understand this behaviour as why on the first > boot, no ramstage log appears and then each successive reset I get the > romstage logs, but not in the first boot. > > Previous sleep state reported in the logs in both the cases is S0. Am > I just missing the logs or there is indeed something happening under > the hood? > > Regards, > Naveen > > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org
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