On Sun, Oct 27, 2019 at 4:29 PM <[email protected]> wrote: > > Hello to all! > Need quick help! I am poorly versed in the question so detailed answers are > welcome :) ! > > As a result of the motherboard developers laziness the hard straps for > ASPEED AST2510 chip were not properly prescribed. > Now I need to write register 0x1e6e2070 with necessary bits [5][15] to '1' at > an early stage of coreboot booting. > Motherboard based on Intel Atom SOC Processor C3758 (DENVERTON_NS). > The AST2510 chip is always located on (B3:D0:F0) [0x1a03:0x2000] after aspeed > bridge (B2:D0:F0) [1a03/1150]: > > PCI: 00:09.0 scanning... > do_pci_scan_bridge for PCI: 00:09.0 > PCI: pci_scan_bus for bus 02 > PCI: 02:00.0 subordinate PCI > PCI: 02:00.0 [1a03/1150] enabled > PCI: 02:00.0 scanning... > do_pci_scan_bridge for PCI: 02:00.0 > PCI: pci_scan_bus for bus 03 > PCI: 03:00.0 [1a03/2000] ops > PCI: 03:00.0 [1a03/2000] enabled > > The code below located in romstage.c file successfully finds the device: > > pci_devfn_t dev; > > /* ASPEED AST2510 Graphics (B3:D0:F0). */ > dev = PCI_DEV(3, 0, 0); > uint32_t id = pci_read_config32(dev, 0); // id = (0x1a03<<16) | > 0x2000 => Aspeed graphics!
Generally, accessing PCI devices on bus other than 0 does not work in romstage. If the above worked, it's probably something the FSP blobs have done. While you could access PCI configuration register of AST2510, you still need to open up IO and/or MMIO windows on the upstream PCI bridge devices as well to achieve the rest. The way things currently work, you don't use struct device in romstage for PCI configuration access. Kyösti _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
