Oops... that buff would get destroyed as its on stack...missed that.
Is there a better way?
Globals are also not getting accepted.
/home/naveen/repos/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: section
.illegal_globals VMA wraps around address space
OBJCOPY ramstage/cpu/x86/smm/smmstub.manual
src/arch/x86/Makefile.inc:246: recipe for target
'build/cbfs/fallback/romstage.debug' failed
Regards,
Naveen
________________________________
From: Naveen Chaudhary <[email protected]>
Sent: Thursday, October 31, 2019 9:46 AM
To: David Hendricks <[email protected]>
Cc: Wim Vervoorn <[email protected]>; Nico Huber <[email protected]>;
[email protected] <[email protected]>
Subject: Re: [coreboot] Re: Coreboot FSP fails to initialize RAM -
"Configuration not in POR table"
Hi,
Do I need to take care of endianness as well?
I made the following change with FSP_MEMORY_DOWN = 0 :
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
index edb313e7d5..822be48ed2 100644
--- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
@@ -77,7 +77,43 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
if (CONFIG(FSP_MEMORY_DOWN)) {
UpdData->MemDownEnable = 1;
- if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT))
+ UINT8 buff[512] = {
+ 0x23, 0x11, 0x0C, 0x06, 0x85, 0x21, 0x00, 0x08, 0x00, 0x60,
0x00, 0x03, 0x09, 0x0B, 0x80, 0x00,
+0x00, 0x00, 0x07, 0x0D, 0xA8, 0x0A, 0x00, 0x00, 0x6E, 0x6E, 0x6E, 0x11, 0x00,
0x6E, 0xF0, 0x0A,
+0x20, 0x08, 0x00, 0x05, 0x00, 0xA8, 0x1B, 0x28, 0x28, 0x00, 0x78, 0x00, 0x14,
0x3C, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C,
0x2C, 0x0C, 0x36,
+0x0C, 0x2C, 0x0C, 0x2C, 0x0C, 0x2C, 0x0C, 0x2C, 0x0C, 0x2C, 0x0C, 0x2C, 0x0C,
0x2C, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0xB5, 0x00, 0x00, 0x00, 0x00, 0xE7,
0xD6, 0xDE, 0xDA,
+0x04, 0x11, 0x1F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xF1, 0x05,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x01, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x53, 0x48, 0x35, 0x37,
0x32, 0x32, 0x47,
+0x38, 0x32, 0x4B, 0x41, 0x4D, 0x46, 0x55, 0x4D, 0x53, 0x42, 0x30, 0x20, 0x20,
0x00, 0x80, 0xCE,
+0x00, 0x53, 0x4D, 0x41, 0x52, 0x54, 0x4D, 0x6F, 0x64, 0x75, 0x6C, 0x61, 0x72,
0x54, 0x65, 0x63,
+0x68, 0x6E, 0x6F, 0x6C, 0x6F, 0x67, 0x69, 0x65, 0x73, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00
+ };
+ UpdData->MemDownCh0Dimm0SpdPtr = (UINT32)(buff);
+ UpdData->MemDownCh1Dimm0SpdPtr = (UINT32)(buff);
+ /*if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT))
UpdData->MemDownCh0Dimm0SpdPtr
= (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin",
CBFS_TYPE_SPD, NULL);
if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT))
@@ -88,10 +124,11 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION
*UpdData)
= (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin",
CBFS_TYPE_SPD, NULL);
if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT))
UpdData->MemDownCh1Dimm1SpdPtr
- = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin",
CBFS_TYPE_SPD, NULL);
+ = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin",
CBFS_TYPE_SPD, NULL);*/
} else {
UpdData->MemDownEnable = 0;
}
But looks like my SPD Data is not read properly because FSP gives me the
following logs. As can be seen I get all zeroes in the mem parameters
bootMode = NormalBoot
subBootMode = ColdBoot
Dispatch Slaves -- Started
Dispatch Slaves - 0ms
Promote Warning Exception List -- Started
Promote Warning Exception List - 0ms
Initialize Throttling Early -- Started
Initialize Throttling Early - 0ms
Detect DIMM Configuration -- Started
Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000
N0: IMC 0 SMB Clock Period = 0x1F2C
Socket | Channel | DIMM | Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
0 | 0 | 0 | 0 | 0 - Present
N0.C0.D0: NVDIMM:N(174)=0xD0
0 | 0 | 1 | 0 | 1 - Not Present
0 | 1 | 0 | 0 | 2 - Present
N0.C1.D0: NVDIMM:N(174)=0xD0
0 | 1 | 1 | 0 | 3 - Not Present
Entering no zone 1
Detect DIMM Configuration - 46ms
Get Slave Data -- Started
Get Slave Data - 0ms
Check POR Compatibility -- Started
primaryWidthDDR4: 0, rowBitsDDR4: 0, columnBitsDDR4: 0, bankGroupsDDR4: 0
N0.C0.D0: DIMM not supported!
A warning has been logged! Warning Code = 0x7, Minor Warning Code = 0x0, Data =
0xFF
S0 Ch0 DIMM0
Warning upgraded to Fatal Error!
FatalError: SocketId = 0 registered Major Code = 0x 7, Minor Code = 0x 0
This is the same SPD data as programmed on the chip which was failing earlier.
I just put the same data in the initial attempt to see if the values are
getting read properly. But why I get all zeros, is this expected?
Regards,
Naveen
________________________________
From: Naveen Chaudhary <[email protected]>
Sent: Wednesday, October 30, 2019 1:01 PM
To: David Hendricks <[email protected]>
Cc: Wim Vervoorn <[email protected]>; Nico Huber <[email protected]>;
[email protected] <[email protected]>
Subject: Re: [coreboot] Re: Coreboot FSP fails to initialize RAM -
"Configuration not in POR table"
Thanks David.
Since some proprietary BIOS already works on this motherboard, this implies
that I can use a different set of settings (timings, latency, etc) to make it
work, as you suggested.
I found that the flag called FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT is there
which I can make use of, to pass an SPD bin. I am not sure how to prepare that
binary but I am assuming we can put all the 512 hex bytes of SPD as per DDR4
SPD spec into a text file and name it as spd.bin and pass along. (example :
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex)
Coreboot build system will automatically pack it. Compilation passed for me
and will test it now, if the SPD data is read properly.
[https://avatars3.githubusercontent.com/u/6484311?s=400&v=4]<https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex>
coreboot/coreboot<https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex>
github mirror of coreboot.org's master repository. Contribute to
coreboot/coreboot development by creating an account on GitHub.
github.com
In case this is not the correct way, the alternative way could be to create a
UINT8 buff [512] and typecast to
UpdData->MemDownCh0Dimm0SpdPtr = (UINT32) buff;
directly.
While I am testing all this, anyone please correct me on the .bin part, so that
it helps future contributors as well, as its not documented anywhere in
coreboot.
Regards,
Naveen
________________________________
From: David Hendricks <[email protected]>
Sent: Wednesday, 30 October, 2019, 12:44 PM
To: Naveen Chaudhary
Cc: Wim Vervoorn; Nico Huber; [email protected]
Subject: Re: [coreboot] Re: Coreboot FSP fails to initialize RAM -
"Configuration not in POR table"
Hi Naveen,
Yes, the first sentence. The DIMMs you are using appear to have geometry or
timings incompatible with Broadwell-DE, based on the SPD values that the vendor
programmed. Chapter 6 of the PDG (docid 543448) should help clarify what kinds
of DIMMs are supported and how they should be populated.
On Tue, Oct 29, 2019 at 5:07 AM Naveen Chaudhary
<[email protected]<mailto:[email protected]>> wrote:
Sorry I didn't get the point completely. Do you mean the settings are not
compatible with FSP code? Or do you mean the settings might be conflicting
themselves.
Since the above settings were read from SPD and the chip vendor must have
definitely set them correctly, I assume you meant first sentence.
Please correct me.
Regards,
Naveen
Get Outlook for Android<https://aka.ms/ghei36>
________________________________
From: Wim Vervoorn <[email protected]<mailto:[email protected]>>
Sent: Tuesday, October 29, 2019 3:47:34 PM
To: Naveen Chaudhary
<[email protected]<mailto:[email protected]>>; Nico
Huber <[email protected]<mailto:[email protected]>>; David Hendricks
<[email protected]<mailto:[email protected]>>
Cc: [email protected]<mailto:[email protected]>
<[email protected]<mailto:[email protected]>>
Subject: RE: [coreboot] Re: Coreboot FSP fails to initialize RAM -
"Configuration not in POR table"
Hello Naveen,
This is the important part. This indicates the what you selected is not
supported.
Please review your settings carefully. This isn't a single check. The code
validates the SPD settings against the other settings you made.
So please make sure you are passing in a DDR4 SPD when you select DDR4 mode.
Also please make sure the SPD settings are in
The list of supported configuration for the chip.
Check POR Compatibility -- Started
primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4
primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4
Unknown DIMM population *****
Check POR Compatibility - 17ms
Initialize DDR Clocks -- Started
Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000
Configuration not in POR table! *** (This basically indicates you are trying
to do something that is not supported by the chipset).
Best regards,
Wim
From: Naveen Chaudhary
[mailto:[email protected]<mailto:[email protected]>]
Sent: Tuesday, October 29, 2019 10:44 AM
To: Wim Vervoorn <[email protected]<mailto:[email protected]>>; Nico Huber
<[email protected]<mailto:[email protected]>>; David Hendricks
<[email protected]<mailto:[email protected]>>
Cc: [email protected]<mailto:[email protected]>
Subject: Re: [coreboot] Re: Coreboot FSP fails to initialize RAM -
"Configuration not in POR table"
Thanks Wim.
I will give a try and pass a 512 byte hex block corresponding to the SPD data
and if it works, I can play with the hex values to find out the right
configuration.
BTW, any idea which field can impact the ddrfreq which was reported as error in
the initial logs?
Regards,
Naveen
Get Outlook for Android<https://aka.ms/ghei36>
________________________________
From: Wim Vervoorn <[email protected]<mailto:[email protected]>>
Sent: Tuesday, October 29, 2019 3:07:44 PM
To: Nico Huber <[email protected]<mailto:[email protected]>>; Naveen Chaudhary
<[email protected]<mailto:[email protected]>>;
David Hendricks <[email protected]<mailto:[email protected]>>
Cc: [email protected]<mailto:[email protected]>
<[email protected]<mailto:[email protected]>>
Subject: RE: [coreboot] Re: Coreboot FSP fails to initialize RAM -
"Configuration not in POR table"
Hello Naveen,
You should use the "MemDownCh0Dimm0SpdPtr" to point to a buffer containing the
SPD data and set MemDownEnable" to 1.
Best Regards,
Wim Vervoorn
-----Original Message-----
From: Nico Huber [mailto:[email protected]]
Sent: Sunday, October 27, 2019 11:33 AM
To: Naveen Chaudhary
<[email protected]<mailto:[email protected]>>;
David Hendricks <[email protected]<mailto:[email protected]>>
Cc: [email protected]<mailto:[email protected]>
Subject: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration
not in POR table"
Hello Naveen,
On 27.10.19 05:02, Naveen Chaudhary wrote:
> Does this mean that there is a way in FSP to define custom settings(configs)
> for DIMMs? In the FSP integration guide for BroadwellDE
> (https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs) I
> don't see any relevant data member where we could define pointer to custom
> SPD settings or pass individual DIMMs configurations.
there is the memory-down option. It seems undocumented if that does more than
switching from on-DIMM SPDs to SPD files. Maybe it's worth a try.
If that doesn't work out, you can always overwrite the SPDs on your DIMM's
EEPROMs. Always keep a backup, though.
Hope that helps,
Nico
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