Dear coreboot community, What are the requirements for working PCIe hotplug support on Intel-based platforms using FSP 2.0?
I see there are FSP configuration options for PCIe root ports hotplug, but setting the bit alone and enabling PCIe hotplug in coreboot is sufficient? Typically there should be an ACPI code or SMI handler to train the link when the device is detected in the slot if I am not mistaken. Anyone with PCIe hotplug experience could advise and clarify my doubts? Thanks in advance. -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com
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