Hi, I want to contribute to the board status database. For this I did a build from 4.11 branch.
This is flashing from the OS for the first time. the SPI command I used was: ./flashrom/flashrom -p ch341a_spi -l firmware/orig/X220/x220-orig.bin.layout -i bios -w coreboot/build/coreboot.rom -c MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F For internal flash I modified this command to this: sudo ./flashrom/flashrom -p internal:boardmismatch=force -l firmware/orig/X220/x220-orig.bin.layout -i bios -w coreboot/build/coreboot.rom -c MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F But it doesn't work. What am I doing wrong? thanks JPT flashrom v1.1-rc1-125-g728062f on Linux 5.4.0-29-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using region: "bios". Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0xbff6a000. Found chipset "Intel QM67". Enabling flash write... SPI Configuration is locked down. FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. FREG2: Management Engine region (0x00003000-0x004fffff) is locked. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. OK. Found Macronix flash chip "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. This coreboot image (LENOVO:ThinkPad X220) does not appear to be correct for the detected mainboard (X220:ThinkPad X220). Proceeding anyway because user forced us to. Reading old flash chip contents... Transaction error! FAILED. _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
