Hi Nico, Nico Huber wrote: > Hi Nitin, > > On 11.06.20 18:44, nitin.ramesh.singh(a)gmail.com wrote: > > Flash start -> 0xFC000000 (with-in 4GB space > > @4227858432) > this is misleading. Setting it in the FMAP makes sense to make the > calculations work, but the flash is not mapped there. > > Because of other fixed resources below 0xff000000, the architectural > limit of memory-mapped flash space is 16MiB. Some chipsets even limit > the mapping to 8MiB. Without making changes to coreboot code (e.g. > switch from memory mapped flash access to using the SPI controller), > all coreboot regions have to fall into the memory mapped space. > I am aware about the given fact... just wanted to describe the way fmap is being arranged. https://www.coreboot.org/Developer_Manual/Memory_map
> > Can any one please let me know what are the other > > changes required to incorporate the Coreboot image as per the given layout? > Generally, such a big CBFS seems odd. I think changes are better made > outside of coreboot, e.g. the payload. What is your exact use case? > > Nico I am using the direct-grub payload (which incorporates cbfs with a limitation of maximum 16MB memory mapped flash space), plus I want to package few other binaries. Thanks, Nitin _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
